ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH344L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH344L

WCHID: C2887250LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH344L (LQFP-48(7x7))1NC2CFG23NC4NC5XI6XO7RESET8GND9VCC10CTS1/GPIO211RTS1/GPIO312TXD113RXD114ACT15TX_S16RX_S17NC18TNOW1/GPIO919TNOW2/GPIO1020GND21TXD222RXD223GND24VCC48VCC47GND46CTS3/GPIO645RTS3/GPIO744TEST43TNOW3/GPIO1142RXD341CTS0/GPIO040RTS0/GPIO139TNOW0/GPIO838CFG37NC36VCC35GND34NC33UD+32UD-31RXD030TXD029TXD328NC27RTS2/GPIO526CTS2/GPIO425NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2CFG2I/OMultiplexed I/O & Peripheral Pin CFG2 (General)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
6XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
7RESETISystem Enable & Hardware Reset (RESET)
8GNDGNDGround Reference Pin (GND)
9VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
10CTS1/GPIO2I/OMultiplexed I/O & Peripheral Pin CTS1/GPIO2 (UART)
11RTS1/GPIO3I/OMultiplexed I/O & Peripheral Pin RTS1/GPIO3 (UART)
12TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
13RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
14ACTI/OMultiplexed I/O & Peripheral Pin ACT (General)
15TX_SI/OMultiplexed I/O & Peripheral Pin TX_S (General)
16RX_SI/OMultiplexed I/O & Peripheral Pin RX_S (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18TNOW1/GPIO9I/OMultiplexed I/O & Peripheral Pin TNOW1/GPIO9 (General)
19TNOW2/GPIO10I/OMultiplexed I/O & Peripheral Pin TNOW2/GPIO10 (General)
20GNDGNDGround Reference Pin (GND)
21TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
22RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
23GNDGNDGround Reference Pin (GND)
24VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
25NCI/OMultiplexed I/O & Peripheral Pin NC (General)
26CTS2/GPIO4I/OMultiplexed I/O & Peripheral Pin CTS2/GPIO4 (UART)
27RTS2/GPIO5I/OMultiplexed I/O & Peripheral Pin RTS2/GPIO5 (UART)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
29TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
30TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
31RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
32UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
33UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35GNDGNDGround Reference Pin (GND)
36VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
37NCI/OMultiplexed I/O & Peripheral Pin NC (General)
38CFGI/OMultiplexed I/O & Peripheral Pin CFG (General)
39TNOW0/GPIO8I/OMultiplexed I/O & Peripheral Pin TNOW0/GPIO8 (General)
40RTS0/GPIO1I/OMultiplexed I/O & Peripheral Pin RTS0/GPIO1 (UART)
41CTS0/GPIO0I/OMultiplexed I/O & Peripheral Pin CTS0/GPIO0 (UART)
42RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
43TNOW3/GPIO11I/OMultiplexed I/O & Peripheral Pin TNOW3/GPIO11 (General)
44TESTI/OMultiplexed I/O & Peripheral Pin TEST (General)
45RTS3/GPIO7I/OMultiplexed I/O & Peripheral Pin RTS3/GPIO7 (UART)
46CTS3/GPIO6I/OMultiplexed I/O & Peripheral Pin CTS3/GPIO6 (UART)
47GNDGNDGround Reference Pin (GND)
48VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH344L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH344L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH344L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH344L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH344L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH344L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH344L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH344
P2 · p02_fig01EXACT PACKAGE
CH344L (LQFP-48(7x7)) — V1.7 2
V1.7 2
P8 · p08_fig01EXACT PACKAGE
CH344L (LQFP-48(7x7)) — 7.1 LQFP48
7.1 LQFP48
P1 · p01_fig011387×530px
CH344L (LQFP-48(7x7)) — 图1-1 系统框图
图1-1 系统框图
P9 · p09_fig011908×1698px
CH344L (LQFP-48(7x7)) — 图8-1 USB 转四路TTL 串口的参考电路图 +5V C2 0.1uF
图8-1 USB 转四路TTL 串口的参考电路图 +5V C2 0.1uF
P9 · p09_fig01P9
CH344L (LQFP-48(7x7)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)

Technical Specifications & Part Details (CH344L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH344L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH344L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH344L (LQFP-48(7x7))?

Manufactured by WCH, the CH344L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (CFG2: Multiplexed I/O & Peripheral Pin CFG2 (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 6 (XO: Multiplexed I/O & Peripheral Pin XO (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH344L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH344L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH344L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH344L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH344 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2CFG2Digital_IOSignal terminal CFG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG2. Supported peripheral buses: General.
3NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
6XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
7RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10CTS1/GPIO2Digital_IOSignal terminal CTS1/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/GPIO2. Supported peripheral buses: UART.
11RTS1/GPIO3Digital_IOSignal terminal RTS1/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/GPIO3. Supported peripheral buses: UART.
12TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
13RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
14ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: General.
15TX_SDigital_IOSignal terminal TX_S (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TX_S. Supported peripheral buses: General.
16RX_SDigital_IOSignal terminal RX_S (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RX_S. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18TNOW1/GPIO9Digital_IOSignal terminal TNOW1/GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1/GPIO9. Supported peripheral buses: General.
19TNOW2/GPIO10Digital_IOSignal terminal TNOW2/GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW2/GPIO10. Supported peripheral buses: General.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
22RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
23GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
24VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
26CTS2/GPIO4Digital_IOSignal terminal CTS2/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2/GPIO4. Supported peripheral buses: UART.
27RTS2/GPIO5Digital_IOSignal terminal RTS2/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS2/GPIO5. Supported peripheral buses: UART.
28NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
29TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
30TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
31RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
32UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
33UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
34NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
36VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
38CFGDigital_IOSignal terminal CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG. Supported peripheral buses: General.
39TNOW0/GPIO8Digital_IOSignal terminal TNOW0/GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW0/GPIO8. Supported peripheral buses: General.
40RTS0/GPIO1Digital_IOSignal terminal RTS0/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/GPIO1. Supported peripheral buses: UART.
41CTS0/GPIO0Digital_IOSignal terminal CTS0/GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0/GPIO0. Supported peripheral buses: UART.
42RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
43TNOW3/GPIO11Digital_IOSignal terminal TNOW3/GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW3/GPIO11. Supported peripheral buses: General.
44TESTDigital_IOSignal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General.
45RTS3/GPIO7Digital_IOSignal terminal RTS3/GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS3/GPIO7. Supported peripheral buses: UART.
46CTS3/GPIO6Digital_IOSignal terminal CTS3/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3/GPIO6. Supported peripheral buses: UART.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
ExplorePartsPackagesMFRsUpload