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CH569W (QFN-68-EP(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH569W

WCHID: C2857462QFN-68-EP(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH569W (QFN-68-EP(8x8))1UD+2UD -3V33USB4SSTXA5SSTXB6P7USB3 0 .8USB3 0 .9P10PA1911PA1812PA813I/O14I/O15I/O16P17I/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25PB1926PB1827PB1728PA1729PB1630PB1531PB1432PB033PB134PB235PA2069GND68XI67XO66GXP65GXM64V33GX63V12CORE62V33LDO61VDDIO60PA1559PA1458PA1357PA1256PA1155PA1054PA953PA2252PA2151PB1350PB1249PB2448PB1147PB2346PB1045PB2244PB943PB842VDDIO41PB740PA1639PB638PB537PB436PB3Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.250.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
2UD -I/OMultiplexed I/O & Peripheral Pin UD - (USB)
3V33USBPowerPower Supply Input (V33USB — 3.3V / 5.0V Standard Logic)
4SSTXAI/OMultiplexed I/O & Peripheral Pin SSTXA (USB)
5SSTXBI/OMultiplexed I/O & Peripheral Pin SSTXB (USB)
6PI/OMultiplexed I/O & Peripheral Pin P (USB)
7USB3 0 .I/OMultiplexed I/O & Peripheral Pin USB3 0 . (USB)
8USB3 0 .I/OMultiplexed I/O & Peripheral Pin USB3 0 . (USB)
9PI/OMultiplexed I/O & Peripheral Pin P (General)
10PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
11PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
13I/OI/OMultiplexed I/O & Peripheral Pin I/O (UART)
14I/OI/OMultiplexed I/O & Peripheral Pin I/O (UART)
15I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
16PI/OMultiplexed I/O & Peripheral Pin P (General)
17I/OI/OMultiplexed I/O & Peripheral Pin I/O (PWM)
18I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
19I/OI/OMultiplexed I/O & Peripheral Pin I/O (UART)
20I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
21I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
22I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
23I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
24I/OI/OMultiplexed I/O & Peripheral Pin I/O (General)
25PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
26PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
27PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
28PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
29PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
30PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
31PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
32PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
33PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
34PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
35PA20I/OMultiplexed I/O & Peripheral Pin PA20 (General)
36PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
37PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
38PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
39PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
40PA16I/OMultiplexed I/O & Peripheral Pin PA16 (General)
41PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
42VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
43PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
44PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
45PB22I/OMultiplexed I/O & Peripheral Pin PB22 (General)
46PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
47PB23I/OMultiplexed I/O & Peripheral Pin PB23 (General)
48PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
49PB24I/OMultiplexed I/O & Peripheral Pin PB24 (General)
50PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
51PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
52PA21I/OMultiplexed I/O & Peripheral Pin PA21 (General)
53PA22I/OMultiplexed I/O & Peripheral Pin PA22 (General)
54PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
55PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
56PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
57PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
58PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
59PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
60PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
61VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
62V33LDOPowerPower Supply Input (V33LDO — 3.3V / 5.0V Standard Logic)
63V12COREI/OMultiplexed I/O & Peripheral Pin V12CORE (General)
64V33GXPowerPower Supply Input (V33GX — 3.3V / 5.0V Standard Logic)
65GXMI/OMultiplexed I/O & Peripheral Pin GXM (General)
66GXPI/OMultiplexed I/O & Peripheral Pin GXP (General)
67XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
68XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
69GNDGNDGround Reference Pin (GND)
PIN 1 UD+
I/O
Multiplexed I/O & Peripheral Pin UD+ (USB)
Design note: DP USB2 0信号线D+ .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH569W (WCH · QFN-68-EP(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH569W (QFN-68-EP(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH569W (QFN-68-EP(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH569W (QFN-68-EP(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH569W (QFN-68-EP(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68-EP(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH569W (QFN-68-EP(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH569W (QFN-68-EP(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH565 / CH569
P119 · p119_fig01EXACT PACKAGE
CH569W (QFN-68-EP(8x8)) — QFN68
QFN68
P1 · p01_fig01247×133px
CH569W (QFN-68-EP(8x8)) — 概述
概述
P2 · p02_fig011438×2370px
CH569W (QFN-68-EP(8x8)) — 图1-1 CH569 和CH565 引脚分布
图1-1 CH569 和CH565 引脚分布
P2 · p02_fig01P2
CH569W (QFN-68-EP(8x8)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011885×1192px
CH569W (QFN-68-EP(8x8)) — V1.3 2 | 1.3 引脚定义 | 1.3.1 CH569 引脚定义 | 表1-2 CH569 引脚定义 | 引脚号 | 引脚 名称 类型 主功能（复位后）/ | 复用功能及映射 功能描述 | 9 V12CORE P V12CORE 系统的1.2V 内核电压输入，需连接到另一个V12CORE 引 脚，外接电容0.1uF | 10 PA19 I/O PA19 /HRCLK | PA19：通用双向数字I/O 引脚 HRCLK：高速并行接口接收采样时钟输入
V1.3 2 | 1.3 引脚定义 | 1.3.1 CH569 引脚定义 | 表1-2 CH569 引脚定义 | 引脚号 | 引脚 名称 类型 主功能（复位后）/ | 复用功能及映射 功能描述 | 9 V12CORE P V12CORE 系统的1.2V 内核电压输入，需连接到另一个V12CORE 引 脚，外接电容0.1uF | 10 PA19 I/O PA19 /HRCLK | PA19：通用双向数字I/O 引脚 HRCLK：高速并行接口接收采样时钟输入
P3 · p03_fig01P3
CH569W (QFN-68-EP(8x8)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P77 · p77_fig01666×504px
CH569W (QFN-68-EP(8x8)) — 图11-1 BUS8接口连接外部芯片 PA8 PA9 PX
图11-1 BUS8接口连接外部芯片 PA8 PA9 PX
P81 · p81_fig011740×1349px
CH569W (QFN-68-EP(8x8)) — 图2-2 时序描述
图2-2 时序描述
P118 · p118_fig011712×455px
CH569W (QFN-68-EP(8x8)) — 测试条件：TA=25℃，VDDLDO=VDDIO=V33USB=V33GX=3.3V，V12CORE=V12USB=1.2V。
测试条件：TA=25℃，VDDLDO=VDDIO=V33USB=V33GX=3.3V，V12CORE=V12USB=1.2V。
P118 · p118_fig021712×1018px
CH569W (QFN-68-EP(8x8)) — 测试条件：TA=25℃，VDDLDO=VDDIO=V33USB=V33GX=3.3V，V12CORE=V12USB=1.2V。
测试条件：TA=25℃，VDDLDO=VDDIO=V33USB=V33GX=3.3V，V12CORE=V12USB=1.2V。
P119 · p119_fig01P119
CH569W (QFN-68-EP(8x8)) — Datasheet Page 119 (p119_fig01)
Datasheet Page 119 (p119_fig01)

Technical Specifications & Part Details (CH569W)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH569W (QFN-68-EP(8x8)) is a 68-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68-EP(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68-EP(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH569W (QFN-68-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH569W (QFN-68-EP(8x8))?

Manufactured by WCH, the CH569W is housed in a QFN-68-EP(8x8) package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 2 (UD -: Multiplexed I/O & Peripheral Pin UD - (USB)), 3 (V33USB: Power Supply Input (V33USB — 3.3V / 5.0V Standard Logic)), 4 (SSTXA: Multiplexed I/O & Peripheral Pin SSTXA (USB)), 5 (SSTXB: Multiplexed I/O & Peripheral Pin SSTXB (USB)), 6 (P: Multiplexed I/O & Peripheral Pin P (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH569W?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH569W (QFN-68-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH569W?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH569W (WCH, QFN-68-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH565 / CH569 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
2UD -Digital_IOSignal terminal UD - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD -. Supported peripheral buses: USB.
3V33USBPower_InPrimary positive power supply input (V33USB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4SSTXADigital_IOSignal terminal SSTXA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSTXA. Supported peripheral buses: USB.
5SSTXBDigital_IOSignal terminal SSTXB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SSTXB. Supported peripheral buses: USB.
6PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: USB.
7USB3 0 .Digital_IOSignal terminal USB3 0 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3 0 .. Supported peripheral buses: USB.
8USB3 0 .Digital_IOSignal terminal USB3 0 . (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB3 0 .. Supported peripheral buses: USB.
9PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: General.
10PA19Digital_IOSignal terminal PA19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA19. Supported peripheral buses: General.
11PA18Digital_IOSignal terminal PA18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA18. Supported peripheral buses: General.
12PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
13I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: UART.
14I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: UART.
15I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
16PDigital_IOSignal terminal P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P. Supported peripheral buses: General.
17I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: PWM.
18I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
19I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: UART.
20I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
21I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
22I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
23I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
24I/ODigital_IOSignal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General.
25PB19Digital_IOSignal terminal PB19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
26PB18Digital_IOSignal terminal PB18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
27PB17Digital_IOSignal terminal PB17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
28PA17Digital_IOSignal terminal PA17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA17. Supported peripheral buses: General.
29PB16Digital_IOSignal terminal PB16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
30PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
31PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
32PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
33PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
34PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
35PA20Digital_IOSignal terminal PA20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA20. Supported peripheral buses: General.
36PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
37PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
38PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
39PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
40PA16Digital_IOSignal terminal PA16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA16. Supported peripheral buses: General.
41PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
42VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
44PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
45PB22Digital_IOSignal terminal PB22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB22. Supported peripheral buses: General.
46PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
47PB23Digital_IOSignal terminal PB23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB23. Supported peripheral buses: General.
48PB11Digital_IOSignal terminal PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
49PB24Digital_IOSignal terminal PB24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB24. Supported peripheral buses: General.
50PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
51PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
52PA21Digital_IOSignal terminal PA21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA21. Supported peripheral buses: General.
53PA22Digital_IOSignal terminal PA22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA22. Supported peripheral buses: General.
54PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
55PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
56PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
57PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
58PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
59PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
60PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
61VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
62V33LDOPower_InPrimary positive power supply input (V33LDO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
63V12COREDigital_IOSignal terminal V12CORE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V12CORE. Supported peripheral buses: General.
64V33GXPower_InPrimary positive power supply input (V33GX) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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