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STM32H523VEI6 (UFBGA-100(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H523VEI6

STID: C28563717UFBGA-100(7x7) · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H523VEI6 (UFBGA-100(7x7))A1PB9A2PB8A3BOOT0A4PB5A5PB3A6PD6A7PD4A8PD3A9PD1A10PC11A11PA15A12PC10B1PE0B2PE4B3PE3B4PB6B5PB4B6PD7B7PD5B8PD2B9PD0B10PC12B11PA14B12PA13C1PE2C2PE5C3VSSC4VCAPC5PB7C8VDDIO2C9VSSC10VDDUSBC11PA12C12PA11D1VBATD2PE6D3VDDD10VDDD11PA10D12PA9E1PC14-OSC32_IE2PC15-OSC32_OE3PC13E10PA8E11PC9E12PC8F1PH0-OSC_INF2PH1-OSC_OUTF11PC7F12PC6M12PB13M11PB10M10PE14M9PE11M8PE9M7PE8M6PE7M5PB0M4PC5M3PC4M2PA5M1PA6L12PB15L11PB12L10PE15L9PE13L8PE10L7VSSL6VDDL5PB2L4PA7L3PA0L2PA4L1PA3K12PD8K11PB14K10VSSK9VCAPK8PE12K5PB1K4PA2K3VSSK2PA1K1VDDAJ12PD10J11PD9J10VDDJ3VDDJ2VSSAJ1VREF+H12PD13H11PD12H10PD11H3PC1H2PC3H1PC2G12PD15G11PD14G2NRSTG1PC0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3H3J3K3L3M3A4B4C4K4L4M4A5B5C5K5L5M5A6B6L6M6A7B7L7M7A8B8C8K8L8M8A9B9C9K9L9M9A10B10C10D10E10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A2PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A3BOOT0IInput-Only Pin BOOT0 (General)
A4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
A8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
A9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
A10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
A11PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A12PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B1PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
B2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
B7PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B11PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
B12PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
C1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
C3VSSGNDGround Reference Pin (VSS)
C4VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
C5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
C8VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
C9VSSGNDGround Reference Pin (VSS)
C10VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
C11PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
D2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
D3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D12PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
E2PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
E3PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
E10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E12PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F1PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
F2PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
F11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
G1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
G2NRSTISystem Enable & Hardware Reset (NRST)
G11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
G12PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H1PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
H2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
H3PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
H10PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
H11PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J2VSSAGNDGround Reference Pin (VSSA)
J3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J11PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
K1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
K3VSSGNDGround Reference Pin (VSS)
K4PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
K5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
K8PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
K9VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
K10VSSGNDGround Reference Pin (VSS)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K12PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
L1PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
L2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
L3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
L4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
L5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
L6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
L7VSSGNDGround Reference Pin (VSS)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
L9PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
L10PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
L11PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
L12PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
M1PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
M2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
M3PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
M4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
M6PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
M11PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
M12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
PIN A1 PB9
I/O
Multiplexed I/O & Peripheral Pin PB9 (General)
Design note: Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H523VEI6 (ST · UFBGA-100(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H523VEI6 (UFBGA-100(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H523VEI6 (UFBGA-100(7x7)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H523VEI6 (UFBGA-100(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H523VEI6 (UFBGA-100(7x7)) - 4. Package Dimensions (D×E×A)
UFBGA-100(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H523VEI6 (UFBGA-100(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H523VEI6 (UFBGA-100(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32H523
P61 · p61_fig01EXACT PACKAGE
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 8. LQFP100 pinout PB9 92
Figure 8. LQFP100 pinout PB9 92
P61 · p61_fig02EXACT PACKAGE
STM32H523VEI6 (UFBGA-100(7x7)) — PB14
PB14
P211 · p211_fig01EXACT PACKAGE
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 71. UFBGA100 - Outline(13) E1 SE
Figure 71. UFBGA100 - Outline(13) E1 SE
P1 · p01_fig011751×1043px
STM32H523VEI6 (UFBGA-100(7x7)) — Memories
Memories
P59 · p59_fig011751×1208px
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 5. LQFP48 pinout VCAP 48 1 2 3
Figure 5. LQFP48 pinout VCAP 48 1 2 3
P59 · p59_fig021546×1193px
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 5. LQFP48 pinout VCAP 48 1 2 3
Figure 5. LQFP48 pinout VCAP 48 1 2 3
P60 · p60_fig011546×988px
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 6. UFQFPN48 pinout VCAP 48 2 3 4
Figure 6. UFQFPN48 pinout VCAP 48 2 3 4
P60 · p60_fig021546×1287px
STM32H523VEI6 (UFBGA-100(7x7)) — VSS
VSS
P61 · p61_fig01P61
STM32H523VEI6 (UFBGA-100(7x7)) — Datasheet Page 61 (p61_fig01)
Datasheet Page 61 (p61_fig01)
P94 · p94_fig011752×2012px
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 14. STM32H523xx/H533xx power supply scheme
Figure 14. STM32H523xx/H533xx power supply scheme
P94 · p94_fig01P94
STM32H523VEI6 (UFBGA-100(7x7)) — Datasheet Page 94 (p94_fig01)
Datasheet Page 94 (p94_fig01)
P117 · p117_fig011546×519px
STM32H523VEI6 (UFBGA-100(7x7)) — Figure 18. Typical application with an 8 MHz crystal
Figure 18. Typical application with an 8 MHz crystal
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32H523VEI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H523VEI6 (UFBGA-100(7x7)) is a 100-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
250 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100(7x7))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-100(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H523VEI6 (UFBGA-100(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H523VEI6 (UFBGA-100(7x7))?

Manufactured by ST, the STM32H523VEI6 is housed in a UFBGA-100(7x7) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A2 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A3 (BOOT0: Input-Only Pin BOOT0 (General)), A4 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A6 (PD6: Multiplexed I/O & Peripheral Pin PD6 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H523VEI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H523VEI6 (UFBGA-100(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H523VEI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H523VEI6 (ST, UFBGA-100(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H523 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A2PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A3BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
A8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
A9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
A10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
A11PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A12PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B1PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
B2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B5PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
B7PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B11PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
B12PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
C1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
C3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C4VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
C5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
C8VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C10VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C11PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
D3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D11PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D12PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
E2PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
E3PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
E10PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F1PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
F2PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
F11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
G1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
G2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
G11PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
G12PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
H1PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
H2PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
H3PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
H10PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
H11PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
H12PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
J1VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
J2VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
J3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
J10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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