STM32H7S3V8T6 (LQFP-100(14x14)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32H7S3V8T6 (LQFP-100(14x14))?

Manufactured by ST, the STM32H7S3V8T6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0 - OSC IN(PH_ 0): Multiplexed I/O & Peripheral Pin PH0 - OSC IN(PH_ 0) (RTC/CLK)), 6 (PH1 - OSC OUT(_ PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC OUT(_ PH1) (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32H7S3V8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7S3V8T6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7S3V8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7S3V8T6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (General)
3	3V3	Power	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	NC	No Connect (Leave Floating)
5	PH0 - OSC IN(PH_ 0)	I/O	Multiplexed I/O & Peripheral Pin PH0 - OSC IN(PH_ 0) (RTC/CLK)
6	PH1 - OSC OUT(_ PH1)	I/O	Multiplexed I/O & Peripheral Pin PH1 - OSC OUT(_ PH1) (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	VSS	GND	Ground Reference Pin (VSS)
9	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
10	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (ADC)
11	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
12	VSSA	GND	Ground Reference Pin (VSSA)
13	VREFM	Analog	Multiplexed I/O & Peripheral Pin VREFM (General)
14	VREFP	Analog	Multiplexed I/O & Peripheral Pin VREFP (General)
15	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
16	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
17	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
18	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
19	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, SPI, ADC, PWM)
20	VSS	GND	Ground Reference Pin (VSS)
21	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
22	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
23	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
24	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
25	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
26	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
27	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
28	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK)
29	PO1	I/O	Multiplexed I/O & Peripheral Pin PO1 (General)
30	VDDXSPI1	Power	Power Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
31	VSS	GND	Ground Reference Pin (VSS)
32	PP4	I/O	Multiplexed I/O & Peripheral Pin PP4 (General)
33	PP2	I/O	Multiplexed I/O & Peripheral Pin PP2 (General)
34	PP3	I/O	Multiplexed I/O & Peripheral Pin PP3 (General)
35	VSS	GND	Ground Reference Pin (VSS)
36	VDDXSPI1	Power	Power Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
37	PO5	I/O	Multiplexed I/O & Peripheral Pin PO5 (General)
38	PO4	I/O	Multiplexed I/O & Peripheral Pin PO4 (General)
39	PP5	I/O	Multiplexed I/O & Peripheral Pin PP5 (General)
40	PP0	I/O	Multiplexed I/O & Peripheral Pin PP0 (General)
41	VSS	GND	Ground Reference Pin (VSS)
42	VDDXSPI1	Power	Power Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
43	PP6	I/O	Multiplexed I/O & Peripheral Pin PP6 (General)
44	PO2	I/O	Multiplexed I/O & Peripheral Pin PO2 (General)
45	PP7	I/O	Multiplexed I/O & Peripheral Pin PP7 (General)
46	PP1	I/O	Multiplexed I/O & Peripheral Pin PP1 (General)
47	VSS	GND	Ground Reference Pin (VSS)
48	VDDXSPI1	Power	Power Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
49	PO0	I/O	Multiplexed I/O & Peripheral Pin PO0 (General)
50	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (General)
51	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (General)
52	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (General)
53	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (General)
54	PE7	I/O	Multiplexed I/O & Peripheral Pin PE7 (General)
55	PE8	I/O	Multiplexed I/O & Peripheral Pin PE8 (PWM)
56	PE9	I/O	Multiplexed I/O & Peripheral Pin PE9 (UART, PWM)
57	PE10	I/O	Multiplexed I/O & Peripheral Pin PE10 (PWM)
58	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
59	VDDLDO	Power	Power Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
60	VSS	GND	Ground Reference Pin (VSS)
61	VCAP1	I/O	Multiplexed I/O & Peripheral Pin VCAP1 (General)
62	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (General)
63	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (General)
64	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (General)
65	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (General)
66	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (General)
67	VCAP3	I/O	Multiplexed I/O & Peripheral Pin VCAP3 (General)
68	VSS	GND	Ground Reference Pin (VSS)
69	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
70	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (General)
71	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (General)
72	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (General)
73	PM0	I/O	Multiplexed I/O & Peripheral Pin PM0 (General)
74	PM1	I/O	Multiplexed I/O & Peripheral Pin PM1 (General)
75	PM2	I/O	Multiplexed I/O & Peripheral Pin PM2 (General)
76	PM3	I/O	Multiplexed I/O & Peripheral Pin PM3 (General)
77	VDD50USB	Power	Power Supply Input (VDD50USB — 3.3V VDD (Max 4.0V))
78	VDD33USB	Power	Power Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
79	VSSUSB	GND	Ground Reference Pin (VSSUSB)
80	PM5	I/O	Multiplexed I/O & Peripheral Pin PM5 (General)
81	PM6	I/O	Multiplexed I/O & Peripheral Pin PM6 (General)
82	DVDD	Power	Power Supply Input (DVDD — 3.3V VDD (Max 4.0V))
83	PM8	I/O	Multiplexed I/O & Peripheral Pin PM8 (General)
84	PM9	I/O	Multiplexed I/O & Peripheral Pin PM9 (General)
85	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
86	PM12	I/O	Multiplexed I/O & Peripheral Pin PM12 (General)
87	PM11	I/O	Multiplexed I/O & Peripheral Pin PM11 (General)
88	PM14	I/O	Multiplexed I/O & Peripheral Pin PM14 (General)
89	PM13	I/O	Multiplexed I/O & Peripheral Pin PM13 (General)
90	BOOT0	I	Input-Only Pin BOOT0 (General)
91	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (General)
92	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
93	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
94	VCAP4	I/O	Multiplexed I/O & Peripheral Pin VCAP4 (General)
95	VSS	GND	Ground Reference Pin (VSS)
96	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
97	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (General)
98	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (General)
99	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
100	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (General)

PIN 1 VBAT

Power

Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))

Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32H7S3V8T6 (LQFP-100(14x14)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32H7S3V8T6 (LQFP-100(14x14)) - 2. Standard Pinout (Top View)

True package pinout (100 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32H7S3V8T6 (LQFP-100(14x14)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32H7S3V8T6 (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)

LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32H7S3V8T6 (LQFP-100(14x14)) - 5. Recommended Land Pattern

IPC-7351B Footprint (100 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32H7S3V8T6 (LQFP-100(14x14)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)

Showing 1–12 of 13 uncropped original figures for STM32H7S7I8T / STM32H7S3V8T / STM32H7S7L8H

P89 · p89_fig01EXACT PACKAGE

Figure 19. LQFP100 GP pinout(a)

P292 · p292_fig01EXACT PACKAGE

Figure 82. LQFP100 - Recommended footprint

P1 · p01_fig01881×841px

• 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.

P76 · p76_fig011751×1342px

Figure 6. TFBGA100 SMPS pinout(a)

P88 · p88_fig011086×1046px

Figure 18. VFQFPN68 GP pinout(a)

P89 · p89_fig01P89

Datasheet Page 89 (p89_fig01)

P153 · p153_fig011619×2259px

Figure 23. Power supply scheme

P153 · p153_fig01P153

Datasheet Page 153 (p153_fig01)

P195 · p195_fig011546×500px

Figure 35. Typical application with an 8 MHz crystal

P196 · p196_fig011546×516px

Figure 36. Typical application with a 32.768 kHz crystal

P289 · p289_fig011559×825px

Figure 80. VFQFPN68 - Recommended footprint

P292 · p292_fig01P292

Datasheet Page 292 (p292_fig01)

Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32H7S3V8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32H7S3V8T6 (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

1.71 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

600 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

19 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

14.00 × 14.00 × 1.55 mm (A1=0.10 mm)

Package family: LQFP (LQFP-100(14x14))

Pin Count & Lead PitchN / e

100 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol100 auto-grouped pins

IPC-7351B Land Pattern100 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

14.00 × 14.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.55mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.20 mm

Pins / Total PadsTopology

100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-100(14x14)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H7S3V8T6 (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H7S3V8T6 (LQFP-100(14x14))?

Manufactured by ST, the STM32H7S3V8T6 is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0 - OSC IN(PH_ 0): Multiplexed I/O & Peripheral Pin PH0 - OSC IN(PH_ 0) (RTC/CLK)), 6 (PH1 - OSC OUT(_ PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC OUT(_ PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32H7S3V8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7S3V8T6 (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7S3V8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7S3V8T6 (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H7S7I8T / STM32H7S3V8T / STM32H7S7L8H Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
3	3V3	Power_In	3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4	NC	No_Connect	No Connect (Leave Floating)
5	PH0 - OSC IN(PH_ 0)	Digital_IO	Signal terminal PH0 - OSC IN(PH_ 0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC IN(PH_ 0). Supported peripheral buses: RTC/CLK.
6	PH1 - OSC OUT(_ PH1)	Digital_IO	Signal terminal PH1 - OSC OUT(_ PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT(_ PH1). Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
11	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
12	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13	VREFM	Analog	Signal terminal VREFM (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREFM. Supported peripheral buses: General.
14	VREFP	Analog	Signal terminal VREFP (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREFP. Supported peripheral buses: General.
15	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
16	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI6_NSS. Supported peripheral buses: UART, SPI, ADC, PWM.
17	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
18	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
19	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI5_RDYSPI1RDY. Supported peripheral buses: UART, SPI, ADC, PWM.
20	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
21	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, ADC.
22	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI6_SCK. Supported peripheral buses: SPI, ADC.
23	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
24	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI6_MISO. Supported peripheral buses: SPI, ADC, PWM.
25	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI6_MOSI. Supported peripheral buses: SPI, ADC, PWM.
26	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
27	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
28	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI, RTC/CLK.
29	PO1	Digital_IO	Signal terminal PO1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO1. Supported peripheral buses: General.
30	VDDXSPI1	Power_In	Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	PP4	Digital_IO	Signal terminal PP4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP4. Supported peripheral buses: General.
33	PP2	Digital_IO	Signal terminal PP2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP2. Supported peripheral buses: General.
34	PP3	Digital_IO	Signal terminal PP3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP3. Supported peripheral buses: General.
35	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
36	VDDXSPI1	Power_In	Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37	PO5	Digital_IO	Signal terminal PO5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO5. Supported peripheral buses: General.
38	PO4	Digital_IO	Signal terminal PO4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO4. Supported peripheral buses: General.
39	PP5	Digital_IO	Signal terminal PP5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP5. Supported peripheral buses: General.
40	PP0	Digital_IO	Signal terminal PP0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP0. Supported peripheral buses: General.
41	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
42	VDDXSPI1	Power_In	Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
43	PP6	Digital_IO	Signal terminal PP6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP6. Supported peripheral buses: General.
44	PO2	Digital_IO	Signal terminal PO2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO2. Supported peripheral buses: General.
45	PP7	Digital_IO	Signal terminal PP7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP7. Supported peripheral buses: General.
46	PP1	Digital_IO	Signal terminal PP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PP1. Supported peripheral buses: General.
47	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48	VDDXSPI1	Power_In	Primary positive power supply input (VDDXSPI1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49	PO0	Digital_IO	Signal terminal PO0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PO0. Supported peripheral buses: General.
50	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
51	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
52	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
53	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
54	PE7	Digital_IO	Signal terminal PE7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
55	PE8	Digital_IO	Signal terminal PE8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: PWM.
56	PE9	Digital_IO	Signal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: UART, PWM.
57	PE10	Digital_IO	Signal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: PWM.
58	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
59	VDDLDO	Power_In	Primary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
60	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
61	VCAP1	Digital_IO	Signal terminal VCAP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP1. Supported peripheral buses: General.
62	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
63	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
64	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.

4D Studio: STM32H7S3V8T6 Permalink: /part/C28314555 ST LQFP-100(14x14)All Packages All Manufacturers