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STM32F401CEY6TR (WLCSP-49) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F401CEY6TR

STID: C2829076WLCSP-49 · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F401CEY6TR (WLCSP-49)A1PA14(JTCK - A2PA15(JTDI)A3PB3 (JTDO SWA4PB4 (NJTRST)A5BOOT0A6VSSA7VDDB1VSSB2VDDB3PA13(JTMS - B4PB5B5PB8B6PDR_ONB7VBATC1PA11C2PA10C3PA12C4PB6C5PB9C6IOC6C7PC14 - OSC32D1PA8D2PA9D3VSSD4PB7G7PA1G6PA4G5PB0G4PB1G3PB2G2VCAP1G1PB13F7VDDAF6PA0F5PA5F4PA6F3PA7F2VDDF1PB14E7NRSTE6VSSA/VREF -E5PA2E4PA3E3PB10E2PB12E1PB15D7PH0OSC IN -_D6PH1 - OSC_OUD5PC13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1A2B2C2D2E2F2G2A3B3C3D3E3F3G3A4B4C4D4E4F4G4A5B5C5D5E5F5G5A6B6C6D6E6F6G6A7B7C7D7E7F7G7E=3.00mm · Pitch e=0.40mmD=3.20mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.20mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA14(JTCK - SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG)
A2PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (SPI, SWD/JTAG)
A3PB3 (JTDO SWO) -I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO SWO) - (SPI, I2C, SWD/JTAG)
A4PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG)
A5BOOT0IInput-Only Pin BOOT0 (General)
A6VSSGNDGround Reference Pin (VSS)
A7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VSSGNDGround Reference Pin (VSS)
B2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B3PA13(JTMS - SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS - SWDIO) (SWD/JTAG)
B4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
B5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B6PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
B7VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART)
C2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
C3PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
C4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, PWM)
C5PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
C6IOC6I/OGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
D2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (I2C, PWM)
D3VSSGNDGround Reference Pin (VSS)
D4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C, PWM)
D5PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
D6PH1 - OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)
D7PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
E1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
E2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
E3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C)
E4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
E5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
E6VSSA/VREF -GNDGround Reference Pin (VSSA/VREF -)
E7NRSTISystem Enable & Hardware Reset (NRST)
F1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
F2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
F4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
F5PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
F6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM)
F7VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
G1PB13I/OMultiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
G2VCAP1I/OMultiplexed I/O & Peripheral Pin VCAP1 (General)
G3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
G5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
G6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
G7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
PIN A1 PA14(JTCK - SWCLK)
I/O
Multiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG)
Design note: Alt: JTCKSWCLK EVENTOUT - ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F401CEY6TR (ST · WLCSP-49)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F401CEY6TR (WLCSP-49) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F401CEY6TR (WLCSP-49) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F401CEY6TR (WLCSP-49) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F401CEY6TR (WLCSP-49) - 4. Package Dimensions (D×E×A)
WLCSP-49 · 3.00×3.20mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F401CEY6TR (WLCSP-49) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F401CEY6TR (WLCSP-49) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for STM32F401
P1 · p01_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces | Datasheet - production data | LQFP100 (14 × 14 mm) | LQFP64 (10 × 10 mm) | UFQFPN48 | (7 × 7 mm) | UFBGA100 | (7 × 7 mm) WLCSP49 (3.06 x 3.0
ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces | Datasheet - production data | LQFP100 (14 × 14 mm) | LQFP64 (10 × 10 mm) | UFQFPN48 | (7 × 7 mm) | UFBGA100 | (7 × 7 mm) WLCSP49 (3.06 x 3.0
P33 · p33_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — Figure 10. STM32F401xD/xE WLCSP49 pinout
Figure 10. STM32F401xD/xE WLCSP49 pinout
P89 · p89_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — 6.3.14 Absolute maximum ratings (electrical sensitivity)
6.3.14 Absolute maximum ratings (electrical sensitivity)
P116 · p116_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — Figure 46. WLCSP49 wafer level chip size package outline
Figure 46. WLCSP49 wafer level chip size package outline
P117 · p117_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint
Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint
P118 · p118_fig01EXACT PACKAGE
STM32F401CEY6TR (WLCSP-49) — Figure 48. Example of WLCSP49 marking (top view)
Figure 48. Example of WLCSP49 marking (top view)
P33 · p33_fig01P33
STM32F401CEY6TR (WLCSP-49) — Datasheet Page 33 (p33_fig01)
Datasheet Page 33 (p33_fig01)
P116 · p116_fig01P116
STM32F401CEY6TR (WLCSP-49) — Datasheet Page 116 (p116_fig01)
Datasheet Page 116 (p116_fig01)
P117 · p117_fig01P117
STM32F401CEY6TR (WLCSP-49) — Datasheet Page 117 (p117_fig01)
Datasheet Page 117 (p117_fig01)
P134 · p134_fig011548×1336px
STM32F401CEY6TR (WLCSP-49) — 9 Revision history
9 Revision history

Technical Specifications & Part Details (STM32F401CEY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F401CEY6TR (WLCSP-49) is a 49-pin embedded microcontroller unit (mcu) featuring a 3.20 × 3.00 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
84 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
38 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.20 × 3.00 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-49)
Pin Count & Lead PitchN / e
49 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-49)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.20 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
49P / 49Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-49
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F401CEY6TR (WLCSP-49)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F401CEY6TR (WLCSP-49)?

Manufactured by ST, the STM32F401CEY6TR is housed in a WLCSP-49 package with 49 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (PA14(JTCK - SWCLK): Multiplexed I/O & Peripheral Pin PA14(JTCK - SWCLK) (SWD/JTAG)), A2 (PA15(JTDI): Multiplexed I/O & Peripheral Pin PA15(JTDI) (SPI, SWD/JTAG)), A3 (PB3 (JTDO SWO) -: Multiplexed I/O & Peripheral Pin PB3 (JTDO SWO) - (SPI, I2C, SWD/JTAG)), A4 (PB4 (NJTRST): Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, I2C, SWD/JTAG)), A5 (BOOT0: Input-Only Pin BOOT0 (General)), A6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for STM32F401CEY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F401CEY6TR (WLCSP-49) has a nominal body envelope of 3.00 × 3.20 mm, pitch e = 0.40 mm, and 49 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F401CEY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F401CEY6TR (ST, WLCSP-49) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32F401 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA14(JTCK - SWCLK)Digital_IOSignal terminal PA14(JTCK - SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK - SWCLK). Supported peripheral buses: SWD/JTAG.
A2PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A3PB3 (JTDO SWO) -Digital_IOSignal terminal PB3 (JTDO SWO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, I2C, SWD/JTAG.
A4PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISOI2S3EXTSD. Supported peripheral buses: SPI, I2C, SWD/JTAG.
A5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PA13(JTMS - SWDIO)Digital_IOSignal terminal PA13(JTMS - SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS - SWDIO). Supported peripheral buses: SWD/JTAG.
B4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
B5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
B6PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
B7VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART.
C2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
C3PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
C4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, PWM.
C5PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, I2C.
C6IOC6Digital_IOGeneral Purpose Digital I/O Pin IOC6
C7PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: I2C, RTC/CLK.
D2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: I2C, PWM.
D3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: I2C, PWM.
D5PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
D6PH1 - OSC_OUT (PH1)Digital_IOSignal terminal PH1 - OSC_OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
D7PH0OSC IN -_ (PH0)Digital_IOSignal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: RTC/CLK.
E1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
E2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, I2C.
E3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, I2C.
E4PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
E5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
E6VSSA/VREF -GND0V electrical ground return terminal (VSSA/VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
E7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOI2S2EXTSD. Supported peripheral buses: SPI, PWM.
F2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSITIM1CH1N. Supported peripheral buses: SPI, ADC, PWM.
F4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOTIM1BKIN. Supported peripheral buses: SPI, ADC, PWM.
F5PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
F6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM.
F7VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, PWM.
G2VCAP1Digital_IOSignal terminal VCAP1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP1. Supported peripheral buses: General.
G3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G4PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
G5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
G6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC.
G7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
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