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C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

C28247518

SemiconductorUFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)A1PC14-OSC32_IA2PC13A3PB9A4PB4A5PB3A6PA15A7PA14A8PA13B1PC15-OSC32_OB2VBATB3PB8B4PH3-BOOT0B5PD2B6PC11B7PC10B8PA12C1PH0-OSC_INC2VSSC3PB7C4PB5C5PC12C6PA10C7PA9C8PA11D1PH1-OSC_OUTD2VDDD3PB6D4VSSD5VSSD6VSSD7PA8D8PC9H8PB12H7VCAPH6PC5H5PC4H4PA7H3PA4H2PA1H1VDDAG8PB13G7PB10G6PB2G5PB1G4PA6G3PA3G2PA0G1PC3F8PB14F7PB15F6PC6F5PB0F4PA5F3PA2F2PC2F1VSSAE8PC8E7PC7E6VDDE5VDDUSBE4VDDE3PC0E2PC1E1NRSTGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8C1C2C3C4C5C6C7C8D1D2D3D4D5D6D7D8E1E2E3E4E5E6E7E8F1F2F3F4F5F6F7F8G1G2G3G4G5G6G7G8H1H2H3H4H5H6H7H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
A2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
A3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A6PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A7PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
A8PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
B1PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
B3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B4PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
B5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B6PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B7PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B8PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C1PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
C2VSSGNDGround Reference Pin (VSS)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
C6PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
C7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
C8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D1PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
D2VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
D3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
D4VSSGNDGround Reference Pin (VSS)
D5VSSGNDGround Reference Pin (VSS)
D6VSSGNDGround Reference Pin (VSS)
D7PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
D8PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
E3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
E4VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
E5VDDUSBPowerPower Supply Input (VDDUSB — 3.3V / 5.0V Standard Logic)
E6VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
E7PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F1VSSAGNDGround Reference Pin (VSSA)
F2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
F3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
F4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
F6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
F8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
G1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
G2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
G3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
G4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
G5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
G6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
G8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
H1VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
H3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
H4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
H5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
H6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
H7VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
H8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
PIN A1 PC14-OSC32_IN
I/O
Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
Design note: Signal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C28247518 (Semiconductor · UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 4. Package Dimensions (D×E×A)
UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C28247518)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) is a 64-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL)?

Manufactured by Semiconductor, the C28247518 is housed in a UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL package with 64 pins and a 0.50 mm lead pitch. Key pins include: A1 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), A2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), A3 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A4 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A6 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)).

What are the IPC-7351B PCB Footprint dimensions for C28247518?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C28247518 (UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C28247518?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C28247518 (Semiconductor, UFBGA-64_L5.0-W5.0-R8-C8-P0.50-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32U535 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
A2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
A3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A6PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A7PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
A8PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
B1PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
B3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B4PH3-BOOT0Digital_IOSignal terminal PH3-BOOT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General.
B5PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B6PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B7PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B8PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C1PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C5PC12Digital_IOSignal terminal PC12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
C6PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
C7PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
C8PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D1PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
D2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
D4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D7PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
D8PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
E3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E5VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E7PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
F3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
F4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
F6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F7PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
F8PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
G1PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
G2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
G3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
G4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
G5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
G6PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G7PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
G8PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
H1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
H3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
H4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
H5PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
H6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
H7VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
H8PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
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