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MX29LV160DBXBI-70GTR (TFBGA) — Symbol, Footprint IPC-7351B & 3D STEP Model

MX29LV160DBXBI-70GTR

MXICID: C2803170TFBGA · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MX29LV160DBXBI-70GTR (TFBGA)A2GNDA3CE#A4A0A5A1A6A2B1Q0B2OE#B3Q8B4A5B5A3B6A4C1Q1C2Q9C3Q10C4A18C5A7C6A6D1Q2D2A19D5WP#/ACCD6A17E1Q3E6NCF1VCCL5A14L4A15L3A16L2Q7L1GNDK6A11K5A13K4A12K3Q11K2Q6K1Q15/A-1J6A9J5A10J4A8J3Q4J2Q5J1Q14H6RESET#H5NCH2BYTE#H1Q13G6WE#G1Q12F6NCGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
L5L4L3L2L1K6K5K4K3K2K1J6J5J4J3J2J1H6H5H2H1G6G1F6F1E6E1D6D5D2D1C6C5C4C3C2C1B6B5B4B3B2B1A6A5A4A3A2E=6.00mm · Pitch e=0.50mmD=4.00mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 6.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A2GNDGNDGround Reference Pin (GND)
A3CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
A4A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
A5A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
A6A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
B1Q0I/OMultiplexed I/O & Peripheral Pin Q0 (General)
B2OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
B3Q8I/OMultiplexed I/O & Peripheral Pin Q8 (General)
B4A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
B5A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
B6A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
C1Q1I/OMultiplexed I/O & Peripheral Pin Q1 (General)
C2Q9I/OMultiplexed I/O & Peripheral Pin Q9 (General)
C3Q10I/OMultiplexed I/O & Peripheral Pin Q10 (General)
C4A18I/OMultiplexed I/O & Peripheral Pin A18 (General)
C5A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
C6A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
D1Q2I/OMultiplexed I/O & Peripheral Pin Q2 (General)
D2A19I/OMultiplexed I/O & Peripheral Pin A19 (General)
D5WP#/ACCI/OMultiplexed I/O & Peripheral Pin WP#/ACC (General)
D6A17I/OMultiplexed I/O & Peripheral Pin A17 (General)
E1Q3I/OMultiplexed I/O & Peripheral Pin Q3 (General)
E6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
F1VCCPowerPower Supply Input (VCC — 2.7 V to 3.6 V)
F6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
G1Q12I/OMultiplexed I/O & Peripheral Pin Q12 (General)
G6WE#I/OMultiplexed I/O & Peripheral Pin WE# (General)
H1Q13I/OMultiplexed I/O & Peripheral Pin Q13 (General)
H2BYTE#I/OMultiplexed I/O & Peripheral Pin BYTE# (General)
H5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
H6RESET#ISystem Enable & Hardware Reset (RESET#)
J1Q14I/OMultiplexed I/O & Peripheral Pin Q14 (General)
J2Q5I/OMultiplexed I/O & Peripheral Pin Q5 (General)
J3Q4I/OMultiplexed I/O & Peripheral Pin Q4 (General)
J4A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
J5A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
J6A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
K1Q15/A-1I/OMultiplexed I/O & Peripheral Pin Q15/A-1 (General)
K2Q6I/OMultiplexed I/O & Peripheral Pin Q6 (General)
K3Q11I/OMultiplexed I/O & Peripheral Pin Q11 (General)
K4A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
K5A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
K6A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
L1GNDGNDGround Reference Pin (GND)
L2Q7I/OMultiplexed I/O & Peripheral Pin Q7 (General)
L3A16I/OMultiplexed I/O & Peripheral Pin A16 (General)
L4A15I/OMultiplexed I/O & Peripheral Pin A15 (General)
L5A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
PIN A2 GND
GND
Ground Reference Pin (GND)
Design note: 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MX29LV160DBXBI-70GTR (MXIC · TFBGA)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MX29LV160DBXBI-70GTR (TFBGA) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MX29LV160DBXBI-70GTR (TFBGA) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MX29LV160DBXBI-70GTR (TFBGA) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MX29LV160DBXBI-70GTR (TFBGA) - 4. Package Dimensions (D×E×A)
TFBGA · 6.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MX29LV160DBXBI-70GTR (TFBGA) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
MX29LV160DBXBI-70GTR (TFBGA) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for MX29LV160DBX / MX29LV160DTX
P7 · p07_fig02EXACT PACKAGE
MX29LV160DBXBI-70GTR (TFBGA) — P/N:PM1315 REV. 1.2, DEC. 22, 2011
P/N:PM1315 REV. 1.2, DEC. 22, 2011
P7 · p07_fig011445×897px
MX29LV160DBXBI-70GTR (TFBGA) — PIN CONFIGURATIONS
PIN CONFIGURATIONS
P7 · p07_fig02P7
MX29LV160DBXBI-70GTR (TFBGA) — Datasheet Page 7 (p07_fig02)
Datasheet Page 7 (p07_fig02)
P9 · p09_fig011781×985px
MX29LV160DBXBI-70GTR (TFBGA) — MX29LV160D T/B
MX29LV160D T/B
P59 · p59_fig011888×2159px
MX29LV160DBXBI-70GTR (TFBGA) — P/N:PM1315 REV. 1.2, DEC. 22, 2011
P/N:PM1315 REV. 1.2, DEC. 22, 2011

Technical Specifications & Part Details (MX29LV160DBXBI-70GTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MX29LV160DBXBI-70GTR (TFBGA) is a 48-pin standard electronic & interconnect component featuring a 4.00 × 6.00 × 1.12 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7 V to 3.6 V supply operation across 0°C to +70°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
2.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to +70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 6.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — MX29LV160DBX / MX29LV160DTX (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TFBGA)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.50mm
Pad Size (W × L)Level B
0.26 × 0.26 mm
Pins / Total PadsTopology
48P / 48Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MX29LV160DBXBI-70GTR (TFBGA)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MX29LV160DBXBI-70GTR (TFBGA)?

Manufactured by MXIC, the MX29LV160DBXBI-70GTR is housed in a TFBGA package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7 V to 3.6 V. Key pins include: A2 (GND: Ground Reference Pin (GND)), A3 (CE#: Multiplexed I/O & Peripheral Pin CE# (General)), A4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), A5 (A1: Multiplexed I/O & Peripheral Pin A1 (General)), A6 (A2: Multiplexed I/O & Peripheral Pin A2 (General)), B1 (Q0: Multiplexed I/O & Peripheral Pin Q0 (General)).

What are the IPC-7351B PCB Footprint dimensions for MX29LV160DBXBI-70GTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MX29LV160DBXBI-70GTR (TFBGA) has a nominal body envelope of 6.00 × 4.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MX29LV160DBXBI-70GTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MX29LV160DBXBI-70GTR (MXIC, TFBGA) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & MX29LV160DBX / MX29LV160DTX Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
A3CE#Digital_IOSignal terminal CE# (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
A4A0Digital_IOSignal terminal A0 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
A5A1Digital_IOSignal terminal A1 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
A6A2Digital_IOSignal terminal A2 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
B1Q0Digital_IOSignal terminal Q0 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q0. Supported peripheral buses: General.
B2OE#Digital_IOSignal terminal OE# (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
B3Q8Digital_IOSignal terminal Q8 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q8. Supported peripheral buses: General.
B4A5Digital_IOSignal terminal A5 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
B5A3Digital_IOSignal terminal A3 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
B6A4Digital_IOSignal terminal A4 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
C1Q1Digital_IOSignal terminal Q1 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q1. Supported peripheral buses: General.
C2Q9Digital_IOSignal terminal Q9 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q9. Supported peripheral buses: General.
C3Q10Digital_IOSignal terminal Q10 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q10. Supported peripheral buses: General.
C4A18Digital_IOSignal terminal A18 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A18. Supported peripheral buses: General.
C5A7Digital_IOSignal terminal A7 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
C6A6Digital_IOSignal terminal A6 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
D1Q2Digital_IOSignal terminal Q2 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q2. Supported peripheral buses: General.
D2A19Digital_IOSignal terminal A19 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A19. Supported peripheral buses: General.
D5WP#/ACCDigital_IOSignal terminal WP#/ACC (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: WP#/ACC. Supported peripheral buses: General.
D6A17Digital_IOSignal terminal A17 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A17. Supported peripheral buses: General.
E1Q3Digital_IOSignal terminal Q3 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q3. Supported peripheral buses: General.
E6NCNCSignal terminal NC (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
F1VCCPower_InPrimary positive power supply input (VCC) operating in the 2.7 V to 3.6 V domain (Max rating: 3.6V).
F6NCNCSignal terminal NC (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
G1Q12Digital_IOSignal terminal Q12 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q12. Supported peripheral buses: General.
G6WE#Digital_IOSignal terminal WE# (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
H1Q13Digital_IOSignal terminal Q13 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q13. Supported peripheral buses: General.
H2BYTE#Digital_IOSignal terminal BYTE# (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: BYTE#. Supported peripheral buses: General.
H5NCNCSignal terminal NC (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
H6RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
J1Q14Digital_IOSignal terminal Q14 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q14. Supported peripheral buses: General.
J2Q5Digital_IOSignal terminal Q5 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q5. Supported peripheral buses: General.
J3Q4Digital_IOSignal terminal Q4 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q4. Supported peripheral buses: General.
J4A8Digital_IOSignal terminal A8 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
J5A10Digital_IOSignal terminal A10 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
J6A9Digital_IOSignal terminal A9 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
K1Q15/A-1Digital_IOSignal terminal Q15/A-1 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q15/A-1. Supported peripheral buses: General.
K2Q6Digital_IOSignal terminal Q6 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q6. Supported peripheral buses: General.
K3Q11Digital_IOSignal terminal Q11 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q11. Supported peripheral buses: General.
K4A12Digital_IOSignal terminal A12 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
K5A13Digital_IOSignal terminal A13 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
K6A11Digital_IOSignal terminal A11 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
L1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
L2Q7Digital_IOSignal terminal Q7 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: Q7. Supported peripheral buses: General.
L3A16Digital_IOSignal terminal A16 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A16. Supported peripheral buses: General.
L4A15Digital_IOSignal terminal A15 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A15. Supported peripheral buses: General.
L5A14Digital_IOSignal terminal A14 (I/O, 2.7 V to 3.6 V domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
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