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STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32U031C8U6

STID: C27889928UFQFPN-48-EP(7x7) · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32U031C8U6 (UFQFPN-48-EP(7x7))1VBAT2PC133PC14-OSC32IN4PC15-OSC32OU5PF0-OSCIN6PF1-OSC_OUT7PF2-NRST8VSSA/VREF-9VDDA/VREF+10PA011PA112PA213PA314PA415PA516PA617PA718PB019PB120PB221PB1022PB1123VSS24VDD25PB1249EP48VDD47VSS46PB945PB844PF3-BOOT0 (B43PB742PB641PB540PB439PB338PA1537PA1436VDD35VSS34PA1333PA12[PA10]32PA11[PA9]31PA1030PA929PA828PB1527PB1426PB13Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3PC14-OSC32INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK)
4PC15-OSC32OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32OUT (RTC/CLK)
5PF0-OSCINI/OMultiplexed I/O & Peripheral Pin PF0-OSCIN (RTC/CLK)
6PF1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)
7PF2-NRSTI/OMultiplexed I/O & Peripheral Pin PF2-NRST (General)
8VSSA/VREF-GNDGround Reference Pin (VSSA/VREF-)
9VDDA/VREF+PowerPower Supply Input (VDDA/VREF+ — 3.3V VDD (Max 4.0V))
10PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
18PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
20PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
23VSSGNDGround Reference Pin (VSS)
24VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
32PA11[PA9]I/OMultiplexed I/O & Peripheral Pin PA11[PA9] (General)
33PA12[PA10]I/OMultiplexed I/O & Peripheral Pin PA12[PA10] (General)
34PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
35VSSGNDGround Reference Pin (VSS)
36VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
42PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
43PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
44PF3-BOOT0 (BOOT0)I/OMultiplexed I/O & Peripheral Pin PF3-BOOT0 (BOOT0) (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
47VSSGNDGround Reference Pin (VSS)
48VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 18 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32U031C8U6 (ST · UFQFPN-48-EP(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 4. Package Dimensions (D×E×A)
UFQFPN-48-EP(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32U031C8U6 (UFQFPN-48-EP(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (18 figures · Page 1/2)
Showing 1–12 of 18 uncropped original figures for STM32U031
P28 · p28_fig01EXACT PACKAGE
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 7. UFQFPN48 pinout
Figure 7. UFQFPN48 pinout
P115 · p115_fig01EXACT PACKAGE
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 41. UFQFPN48 - Outline
Figure 41. UFQFPN48 - Outline
P116 · p116_fig01EXACT PACKAGE
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
P116 · p116_fig02EXACT PACKAGE
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 42. UFQFPN48 - Footprint example
Figure 42. UFQFPN48 - Footprint example
P1 · p01_fig011408×522px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — • 430 ULPMark™-CP
• 430 ULPMark™-CP
P26 · p26_fig01941×538px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 3. TSSOP20 pinout
Figure 3. TSSOP20 pinout
P26 · p26_fig021533×708px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 4. WLCSP27 ballout
Figure 4. WLCSP27 ballout
P28 · p28_fig01P28
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)
P40 · p40_fig011436×1189px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P40 · p40_fig01P40
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Datasheet Page 40 (p40_fig01)
Datasheet Page 40 (p40_fig01)
P68 · p68_fig011432×511px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 17. Typical application with an 8 MHz crystal
Figure 17. Typical application with an 8 MHz crystal
P87 · p87_fig01908×757px
STM32U031C8U6 (UFQFPN-48-EP(7x7)) — Figure 24. ADC accuracy characteristics
Figure 24. ADC accuracy characteristics
Page 1 / 2 (18 extracted figures)

Technical Specifications & Part Details (STM32U031C8U6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32U031C8U6 (UFQFPN-48-EP(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
8 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-48-EP(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PF3-BOOT0 (BOOT0)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-48-EP(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-48-EP(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U031C8U6 (UFQFPN-48-EP(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U031C8U6 (UFQFPN-48-EP(7x7))?

Manufactured by ST, the STM32U031C8U6 is housed in a UFQFPN-48-EP(7x7) package with 49 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14-OSC32IN: Multiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK)), 4 (PC15-OSC32OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32OUT (RTC/CLK)), 5 (PF0-OSCIN: Multiplexed I/O & Peripheral Pin PF0-OSCIN (RTC/CLK)), 6 (PF1-OSC_OUT: Multiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32U031C8U6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U031C8U6 (UFQFPN-48-EP(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U031C8U6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U031C8U6 (ST, UFQFPN-48-EP(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32U031 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3PC14-OSC32INDigital_IOSignal terminal PC14-OSC32IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14-OSC32IN. Supported peripheral buses: RTC/CLK.
4PC15-OSC32OUTDigital_IOSignal terminal PC15-OSC32OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15-OSC32OUT. Supported peripheral buses: RTC/CLK.
5PF0-OSCINDigital_IOSignal terminal PF0-OSCIN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0-OSCIN. Supported peripheral buses: RTC/CLK.
6PF1-OSC_OUTDigital_IOSignal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK.
7PF2-NRSTDigital_IOSignal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General.
8VSSA/VREF-GND0V electrical ground return terminal (VSSA/VREF-) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDA/VREF+Power_InPrimary positive power supply input (VDDA/VREF+) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
10PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
11PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
12PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
13PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
14PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
15PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
16PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
17PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
18PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
19PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
20PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
21PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
22PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
23VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
28PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
29PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
30PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
32PA11[PA9]Digital_IOSignal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General.
33PA12[PA10]Digital_IOSignal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General.
34PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
35VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
36VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
37PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
42PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
43PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
44PF3-BOOT0 (BOOT0)Digital_IOSignal terminal PF3-BOOT0 (BOOT0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3-BOOT0 (BOOT0). Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
46PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: SPI, I2C.
47VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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