ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH9344L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9344L

WCHID: C2762852LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9344L (LQFP-48(7x7))1GND2VCC333V12O4NC5NC6NC7NC8NC9NC10NC11CTS1/GPIO312RTS1/GPIO413CTS2/GPIO614RTS2/GPIO715CTS3/GPIO916RTS3/GPIO1017TEST18VIO119TXD020RTS0/GPIO121DTR022RXD023DCD024RI048VIO247TNOW3/GPIO1146TNOW2/GPIO845TXD144RXD143TXD242RXD241TXD340RXD339TNOW1/GPIO538RST#37ISP36TNOW0/GPIO235V12I34GND33VCC3332UD -31UD+30RSVD129XI28XO27VCC3326CTS0/GPIO025DSR0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
3V12OI/OMultiplexed I/O & Peripheral Pin V12O (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9NCI/OMultiplexed I/O & Peripheral Pin NC (General)
10NCI/OMultiplexed I/O & Peripheral Pin NC (General)
11CTS1/GPIO3I/OMultiplexed I/O & Peripheral Pin CTS1/GPIO3 (UART)
12RTS1/GPIO4I/OMultiplexed I/O & Peripheral Pin RTS1/GPIO4 (UART)
13CTS2/GPIO6I/OMultiplexed I/O & Peripheral Pin CTS2/GPIO6 (UART)
14RTS2/GPIO7I/OMultiplexed I/O & Peripheral Pin RTS2/GPIO7 (UART)
15CTS3/GPIO9I/OMultiplexed I/O & Peripheral Pin CTS3/GPIO9 (UART)
16RTS3/GPIO10I/OMultiplexed I/O & Peripheral Pin RTS3/GPIO10 (UART)
17TESTI/OMultiplexed I/O & Peripheral Pin TEST (General)
18VIO1I/OMultiplexed I/O & Peripheral Pin VIO1 (General)
19TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
20RTS0/GPIO1I/OMultiplexed I/O & Peripheral Pin RTS0/GPIO1 (UART)
21DTR0I/OMultiplexed I/O & Peripheral Pin DTR0 (UART)
22RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
23DCD0I/OMultiplexed I/O & Peripheral Pin DCD0 (General)
24RI0I/OMultiplexed I/O & Peripheral Pin RI0 (General)
25DSR0I/OMultiplexed I/O & Peripheral Pin DSR0 (UART)
26CTS0/GPIO0I/OMultiplexed I/O & Peripheral Pin CTS0/GPIO0 (UART)
27VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
28XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
29XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
30RSVD1I/OMultiplexed I/O & Peripheral Pin RSVD1 (General)
31UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
32UD -I/OMultiplexed I/O & Peripheral Pin UD - (USB)
33VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
34GNDGNDGround Reference Pin (GND)
35V12II/OMultiplexed I/O & Peripheral Pin V12I (General)
36TNOW0/GPIO2I/OMultiplexed I/O & Peripheral Pin TNOW0/GPIO2 (General)
37ISPI/OMultiplexed I/O & Peripheral Pin ISP (General)
38RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
39TNOW1/GPIO5I/OMultiplexed I/O & Peripheral Pin TNOW1/GPIO5 (General)
40RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
41TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
42RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
43TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
44RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
45TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
46TNOW2/GPIO8I/OMultiplexed I/O & Peripheral Pin TNOW2/GPIO8 (General)
47TNOW3/GPIO11I/OMultiplexed I/O & Peripheral Pin TNOW3/GPIO11 (General)
48VIO2I/OMultiplexed I/O & Peripheral Pin VIO2 (General)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: Ground:publicground 0Vreferencepoint , .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9344L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9344L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9344L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9344L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9344L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9344L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9344L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH9344
P1 · p01_fig011531×623px
CH9344L (LQFP-48(7x7)) — 2. Features
2. Features
P2 · p02_fig01967×958px
CH9344L (LQFP-48(7x7)) — 3. Packages
3. Packages
P2 · p02_fig01P2
CH9344L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P6 · p06_fig011585×1385px
CH9344L (LQFP-48(7x7)) — 7.1 USB to Quad-TTL UART Interfaces
7.1 USB to Quad-TTL UART Interfaces

Technical Specifications & Part Details (CH9344L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9344L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9344L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9344L (LQFP-48(7x7))?

Manufactured by WCH, the CH9344L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (VCC33: Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)), 3 (V12O: Multiplexed I/O & Peripheral Pin V12O (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9344L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9344L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9344L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9344L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH9344 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3V12ODigital_IOSignal terminal V12O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V12O. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
11CTS1/GPIO3Digital_IOSignal terminal CTS1/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/GPIO3. Supported peripheral buses: UART.
12RTS1/GPIO4Digital_IOSignal terminal RTS1/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/GPIO4. Supported peripheral buses: UART.
13CTS2/GPIO6Digital_IOSignal terminal CTS2/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2/GPIO6. Supported peripheral buses: UART.
14RTS2/GPIO7Digital_IOSignal terminal RTS2/GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS2/GPIO7. Supported peripheral buses: UART.
15CTS3/GPIO9Digital_IOSignal terminal CTS3/GPIO9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3/GPIO9. Supported peripheral buses: UART.
16RTS3/GPIO10Digital_IOSignal terminal RTS3/GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS3/GPIO10. Supported peripheral buses: UART.
17TESTDigital_IOSignal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General.
18VIO1Digital_IOSignal terminal VIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO1. Supported peripheral buses: General.
19TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
20RTS0/GPIO1Digital_IOSignal terminal RTS0/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/GPIO1. Supported peripheral buses: UART.
21DTR0Digital_IOSignal terminal DTR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0. Supported peripheral buses: UART.
22RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
23DCD0Digital_IOSignal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General.
24RI0Digital_IOSignal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
25DSR0Digital_IOSignal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART.
26CTS0/GPIO0Digital_IOSignal terminal CTS0/GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0/GPIO0. Supported peripheral buses: UART.
27VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
29XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
30RSVD1Digital_IOSignal terminal RSVD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD1. Supported peripheral buses: General.
31UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
32UD -Digital_IOSignal terminal UD - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD -. Supported peripheral buses: USB.
33VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35V12IDigital_IOSignal terminal V12I (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V12I. Supported peripheral buses: General.
36TNOW0/GPIO2Digital_IOSignal terminal TNOW0/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW0/GPIO2. Supported peripheral buses: General.
37ISPDigital_IOSignal terminal ISP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISP. Supported peripheral buses: General.
38RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
39TNOW1/GPIO5Digital_IOSignal terminal TNOW1/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW1/GPIO5. Supported peripheral buses: General.
40RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
41TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
42RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
43TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
44RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
45TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
46TNOW2/GPIO8Digital_IOSignal terminal TNOW2/GPIO8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW2/GPIO8. Supported peripheral buses: General.
47TNOW3/GPIO11Digital_IOSignal terminal TNOW3/GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TNOW3/GPIO11. Supported peripheral buses: General.
48VIO2Digital_IOSignal terminal VIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO2. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload