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CH9141 (QFN-28-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9141

WCHID: C2693433QFN-28-EP(4x4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9141 (QFN-28-EP(4x4))1X32KO2X32KI3VDD_D4VSW5VCC6AT7ADC8DCD#/GPIO79DSR#/GPIO610RI#/GPIO511DTR#/BLESTA/12RTS#/TNOW13CTS#14TXD15RXD29GND28GPIO027GPIO126GPIO225GPIO324SLEEP23RELOAD/LED22VDD_A21ANT20VINTA19X32MI18X32MO17NC16RST#Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1X32KOI/OMultiplexed I/O & Peripheral Pin X32KO (General)
2X32KII/OMultiplexed I/O & Peripheral Pin X32KI (General)
3VDD_DPowerPower Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)
4VSWI/OMultiplexed I/O & Peripheral Pin VSW (General)
5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
6ATI/OMultiplexed I/O & Peripheral Pin AT (General)
7ADCI/OMultiplexed I/O & Peripheral Pin ADC (ADC)
8DCD#/GPIO7I/OMultiplexed I/O & Peripheral Pin DCD#/GPIO7 (General)
9DSR#/GPIO6I/OMultiplexed I/O & Peripheral Pin DSR#/GPIO6 (UART)
10RI#/GPIO5I/OMultiplexed I/O & Peripheral Pin RI#/GPIO5 (General)
11DTR#/BLESTA/GPIO4I/OMultiplexed I/O & Peripheral Pin DTR#/BLESTA/GPIO4 (UART)
12RTS#/TNOWI/OMultiplexed I/O & Peripheral Pin RTS#/TNOW (UART)
13CTS#I/OMultiplexed I/O & Peripheral Pin CTS# (UART)
14TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
15RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
16RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18X32MOI/OMultiplexed I/O & Peripheral Pin X32MO (General)
19X32MII/OMultiplexed I/O & Peripheral Pin X32MI (General)
20VINTAPowerPower Supply Input (VINTA — 3.3V / 5.0V Standard Logic)
21ANTI/OMultiplexed I/O & Peripheral Pin ANT (General)
22VDD_APowerPower Supply Input (VDD_A — 3.3V / 5.0V Standard Logic)
23RELOAD/LEDI/OMultiplexed I/O & Peripheral Pin RELOAD/LED (General)
24SLEEPI/OMultiplexed I/O & Peripheral Pin SLEEP (General)
25GPIO3I/OMultiplexed I/O & Peripheral Pin GPIO3 (General)
26GPIO2I/OMultiplexed I/O & Peripheral Pin GPIO2 (General)
27GPIO1I/OMultiplexed I/O & Peripheral Pin GPIO1 (General)
28GPIO0I/OMultiplexed I/O & Peripheral Pin GPIO0 (General)
29GNDGNDGround Reference Pin (GND)
PIN 1 X32KO
I/O
Multiplexed I/O & Peripheral Pin X32KO (General)
Design note: Signal terminal X32KO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KO. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9141 (WCH · QFN-28-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9141 (QFN-28-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9141 (QFN-28-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9141 (QFN-28-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9141 (QFN-28-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9141 (QFN-28-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9141 (QFN-28-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH9141
P2 · p02_fig01EXACT PACKAGE
CH9141 (QFN-28-EP(4x4)) — Model | Package | Name Description | CH9141 QFN28 4*4mm | CH9141K ESSOP10 6*5mm | 4. Pins | QFN28 Pin No. | ESSOP10 | Pin No. Pin Name Pin Type Description | 0 0 GND P Ground | 1 | None | X32K0 A Inverted output of low-frequency crystal osc
Model | Package | Name Description | CH9141 QFN28 4*4mm | CH9141K ESSOP10 6*5mm | 4. Pins | QFN28 Pin No. | ESSOP10 | Pin No. Pin Name Pin Type Description | 0 0 GND P Ground | 1 | None | X32K0 A Inverted output of low-frequency crystal osc
P1 · p01_fig011487×396px
CH9141 (QFN-28-EP(4x4)) — Figure 1 Block Diagram of Serial Communication between BLE Host and Serial Port Devices through CH9141 Figure 2 Block Diagram of communication between MCUs or Serial Port Devices on Both Ends through
Figure 1 Block Diagram of Serial Communication between BLE Host and Serial Port Devices through CH9141 Figure 2 Block Diagram of communication between MCUs or Serial Port Devices on Both Ends through
P1 · p01_fig021707×602px
CH9141 (QFN-28-EP(4x4)) — Figure 1 Block Diagram of Serial Communication between BLE Host and Serial Port Devices through CH9141 Figure 2 Block Diagram of communication between MCUs or Serial Port Devices on Both Ends through
Figure 1 Block Diagram of Serial Communication between BLE Host and Serial Port Devices through CH9141 Figure 2 Block Diagram of communication between MCUs or Serial Port Devices on Both Ends through
P2 · p02_fig01P2
CH9141 (QFN-28-EP(4x4)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)

Technical Specifications & Part Details (CH9141)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9141 (QFN-28-EP(4x4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, UART, ADC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, UART, ADC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (GPIO0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9141 (QFN-28-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9141 (QFN-28-EP(4x4))?

Manufactured by WCH, the CH9141 is housed in a QFN-28-EP(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (X32KO: Multiplexed I/O & Peripheral Pin X32KO (General)), 2 (X32KI: Multiplexed I/O & Peripheral Pin X32KI (General)), 3 (VDD_D: Power Supply Input (VDD_D — 3.3V / 5.0V Standard Logic)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 6 (AT: Multiplexed I/O & Peripheral Pin AT (General)).

What are the IPC-7351B PCB Footprint dimensions for CH9141?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9141 (QFN-28-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9141?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9141 (WCH, QFN-28-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH9141 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1X32KODigital_IOSignal terminal X32KO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KO. Supported peripheral buses: General.
2X32KIDigital_IOSignal terminal X32KI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32KI. Supported peripheral buses: General.
3VDD_DPower_InPrimary positive power supply input (VDD_D) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4VSWDigital_IOSignal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6ATDigital_IOSignal terminal AT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AT. Supported peripheral buses: General.
7ADCAnalogSignal terminal ADC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADC. Supported peripheral buses: ADC.
8DCD#/GPIO7Digital_IOSignal terminal DCD#/GPIO7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD#/GPIO7. Supported peripheral buses: General.
9DSR#/GPIO6Digital_IOSignal terminal DSR#/GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR#/GPIO6. Supported peripheral buses: UART.
10RI#/GPIO5Digital_IOSignal terminal RI#/GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI#/GPIO5. Supported peripheral buses: General.
11DTR#/BLESTA/GPIO4Digital_IOSignal terminal DTR#/BLESTA/GPIO4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR#/BLESTA/GPIO4. Supported peripheral buses: UART.
12RTS#/TNOWDigital_IOSignal terminal RTS#/TNOW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS#/TNOW. Supported peripheral buses: UART.
13CTS#Digital_IOSignal terminal CTS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS#. Supported peripheral buses: UART.
14TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
15RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
16RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
17NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18X32MODigital_IOSignal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General.
19X32MIDigital_IOSignal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General.
20VINTAPower_InPrimary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21ANTRF_50OhmSignal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General.
22VDD_APower_InPrimary positive power supply input (VDD_A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23RELOAD/LEDDigital_IOSignal terminal RELOAD/LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RELOAD/LED. Supported peripheral buses: General.
24SLEEPDigital_IOSignal terminal SLEEP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLEEP. Supported peripheral buses: General.
25GPIO3Digital_IOSignal terminal GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO3. Supported peripheral buses: General.
26GPIO2Digital_IOSignal terminal GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
27GPIO1Digital_IOSignal terminal GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO1. Supported peripheral buses: General.
28GPIO0Digital_IOSignal terminal GPIO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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