Mechanical Dimensions & Land Pattern (SSOP-10-EP-150mil)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SSOP-10-EP-150mil | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KP18062ESPA (SSOP-10-EP-150mil)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KP18062ESPA (SSOP-10-EP-150mil)?
Manufactured by Kiwi Instruments, the KP18062ESPA is housed in a SSOP-10-EP-150mil package with 11 pins and a 1.00 mm lead pitch. Key pins include: 1 (PWM1: Multiplexed I/O & Peripheral Pin PWM1 (PWM)), 2 (RCS1: Multiplexed I/O & Peripheral Pin RCS1 (General)), 3 (PWM2: Multiplexed I/O & Peripheral Pin PWM2 (PWM)), 4 (RCS2: Multiplexed I/O & Peripheral Pin RCS2 (General)), 5 (RSL: Multiplexed I/O & Peripheral Pin RSL (General)), 6 (COUT: Multiplexed I/O & Peripheral Pin COUT (General)).
What are the IPC-7351B PCB Footprint dimensions for KP18062ESPA?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP18062ESPA (SSOP-10-EP-150mil) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.00 mm, and 11 copper pads plus a central exposed thermal pad (EPAD) of 2.10 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP18062ESPA?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP18062ESPA (Kiwi Instruments, SSOP-10-EP-150mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (11 pins) & KP18062 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PWM1 | Digital_IO | Signal terminal PWM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM1. Supported peripheral buses: PWM. |
| 2 | RCS1 | Digital_IO | Signal terminal RCS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RCS1. Supported peripheral buses: General. |
| 3 | PWM2 | Digital_IO | Signal terminal PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM2. Supported peripheral buses: PWM. |
| 4 | RCS2 | Digital_IO | Signal terminal RCS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RCS2. Supported peripheral buses: General. |
| 5 | RSL | Digital_IO | Signal terminal RSL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSL. Supported peripheral buses: General. |
| 6 | COUT | Digital_IO | Signal terminal COUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COUT. Supported peripheral buses: General. |
| 7 | LED2 | Digital_IO | Signal terminal LED2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED2. Supported peripheral buses: General. |
| 8 | LED1 | Digital_IO | Signal terminal LED1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED1. Supported peripheral buses: General. |
| 9 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 10 | Vin | Power_In | Primary positive power supply input (Vin) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |