ESOP-8 · 9P
Synchronized Pinout (Symbol / 2D / 3D) (9/9)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 2 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 3 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 4 | OUT | I/O | Multiplexed I/O & Peripheral Pin OUT (General) |
| 5 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 6 | CS | I/O | Multiplexed I/O & Peripheral Pin CS (General) |
| 7 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 8 | TEMP | I/O | Multiplexed I/O & Peripheral Pin TEMP (General) |
| 9 | EP | GND | Exposed Thermal & Ground Pad (EP) |
PIN 1 NC
I/OMultiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (9 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ESOP-8 · 3.90×4.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (9 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for KP18002
P1 · p01_fig01EXACT PACKAGE
P2 · p02_fig01EXACT PACKAGE
P4 · p04_fig01EXACT PACKAGE
P1 · p01_fig01P1
P2 · p02_fig02402×401px
P2 · p02_fig03396×395px
P2 · p02_fig01P2
P2 · p02_fig02P2
P4 · p04_fig01P4
Technical Specifications & Part Details (KP18002ESPA)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:KP18002ESPA (ESOP-8) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.70 mm (A1=0.10 mm)
Package family: SOP (ESOP-8)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol9 auto-grouped pins
IPC-7351B Land Pattern9 pads · Pitch 1.27mm
IPC-7525 60% Solder PasteEPAD 2.40×3.30mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — KP18002 (2)
ESOP-8 · 9P
Mechanical Dimensions & Land Pattern (ESOP-8)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
9P / 9Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit ESOP-8 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — KP18002ESPA (ESOP-8)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of KP18002ESPA (ESOP-8)?
Manufactured by Kiwi Instruments, the KP18002ESPA is housed in a ESOP-8 package with 9 pins and a 1.27 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (OUT: Multiplexed I/O & Peripheral Pin OUT (General)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (CS: Multiplexed I/O & Peripheral Pin CS (General)).
What are the IPC-7351B PCB Footprint dimensions for KP18002ESPA?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), KP18002ESPA (ESOP-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.40 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for KP18002ESPA?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for KP18002ESPA (Kiwi Instruments, ESOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (9 pins) & KP18002 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 2 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 3 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 4 | OUT | Digital_IO | Signal terminal OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT. Supported peripheral buses: General. |
| 5 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 6 | CS | Digital_IO | Signal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General. |
| 7 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 8 | TEMP | Digital_IO | Signal terminal TEMP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEMP. Supported peripheral buses: General. |
| 9 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |