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CH32F103C8T6 (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32F103C8T6

WCHID: C2687451LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32F103C8T6 (LQFP-48(7x7))1VBAT2PC13 - TAMPE3PC14 - OSC324PC15 - OSC325OSC8M_IN6OSC8M_OUT7NRST8VSSA9VDDA10PA0 WKUP -11PA112PA213PA314PA415PA516PA617PA718PB019PB120PB221PB1022PB1123VSS1_24VDD1_48VDD3_47VSS3_46PB945PB844BOOT043PB742PB641PB540PB439PB338PA1537PA1436VDD2_35VSS2_34PA1333PA1232PA1131PA1030PA929PA828PB1527PB1426PB1325PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 2.7V~5.5V)
2PC13 - TAMPER RTC -I/OMultiplexed I/O & Peripheral Pin PC13 - TAMPER RTC - (RTC/CLK)
3PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
4PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
5OSC8M_INI/OMultiplexed I/O & Peripheral Pin OSC8M_IN (RTC/CLK)
6OSC8M_OUTI/OMultiplexed I/O & Peripheral Pin OSC8M_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 2.7V~5.5V)
10PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (General)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
18PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
20PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
22PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
23VSS1_GNDGround Reference Pin (VSS1_)
24VDD1_PowerPower Supply Input (VDD1_ — 2.7V~5.5V)
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
32PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
33PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
34PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
35VSS2_GNDGround Reference Pin (VSS2_)
36VDD2_PowerPower Supply Input (VDD2_ — 2.7V~5.5V)
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
42PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
43PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
46PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
47VSS3_GNDGround Reference Pin (VSS3_)
48VDD3_PowerPower Supply Input (VDD3_ — 2.7V~5.5V)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 2.7V~5.5V)
Design note: Primary positive power supply input (VBAT) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32F103C8T6 (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32F103C8T6 (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32F103C8T6 (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32F103C8T6 (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32F103C8T6 (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32F103C8T6 (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32F103C8T6 (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32F103
P11 · p11_fig01EXACT PACKAGE
CH32F103C8T6 (LQFP-48(7x7)) — 图2-1 CH32F103Cx（LQFP48/QFN48X7）引脚分布
图2-1 CH32F103Cx（LQFP48/QFN48X7）引脚分布
P11 · p11_fig02EXACT PACKAGE
CH32F103C8T6 (LQFP-48(7x7)) — 图2-2 CH32F103Rx（LQFP64M）引脚分布
图2-2 CH32F103Rx（LQFP64M）引脚分布
P28 · p28_fig01EXACT PACKAGE
CH32F103C8T6 (LQFP-48(7x7)) — 图4-1 LQFP48 封装
图4-1 LQFP48 封装
P1 · p01_fig01245×132px
CH32F103C8T6 (LQFP-48(7x7)) — 概述
概述
P28 · p28_fig02906×687px
CH32F103C8T6 (LQFP-48(7x7)) — 图4-2 QFN48X7（QFN48-7*7）封装
图4-2 QFN48X7（QFN48-7*7）封装
P28 · p28_fig02P28
CH32F103C8T6 (LQFP-48(7x7)) — Datasheet Page 28 (p28_fig02)
Datasheet Page 28 (p28_fig02)

Technical Specifications & Part Details (CH32F103C8T6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32F103C8T6 (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V~5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, CAN, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V~5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
16MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, CAN, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32F103C8T6 (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32F103C8T6 (LQFP-48(7x7))?

Manufactured by WCH, the CH32F103C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V~5.5V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 2.7V~5.5V)), 2 (PC13 - TAMPER RTC -: Multiplexed I/O & Peripheral Pin PC13 - TAMPER RTC - (RTC/CLK)), 3 (PC14 - OSC32_IN: Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)), 4 (PC15 - OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)), 5 (OSC8M_IN: Multiplexed I/O & Peripheral Pin OSC8M_IN (RTC/CLK)), 6 (OSC8M_OUT: Multiplexed I/O & Peripheral Pin OSC8M_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32F103C8T6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32F103C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32F103C8T6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32F103C8T6 (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
2PC13 - TAMPER RTC -Digital_IOSignal terminal PC13 - TAMPER RTC - (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC13 - TAMPER RTC -. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
4PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
5OSC8M_INDigital_IOSignal terminal OSC8M_IN (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: OSC8M_IN. Supported peripheral buses: RTC/CLK.
6OSC8M_OUTDigital_IOSignal terminal OSC8M_OUT (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: OSC8M_OUT. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
10PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: General.
11PA1Digital_IOSignal terminal PA1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
12PA2Digital_IOSignal terminal PA2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
13PA3Digital_IOSignal terminal PA3 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
14PA4Digital_IOSignal terminal PA4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
15PA5Digital_IOSignal terminal PA5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
16PA6Digital_IOSignal terminal PA6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
17PA7Digital_IOSignal terminal PA7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
18PB0Digital_IOSignal terminal PB0 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
19PB1Digital_IOSignal terminal PB1 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
20PB2Digital_IOSignal terminal PB2 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
21PB10Digital_IOSignal terminal PB10 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
22PB11Digital_IOSignal terminal PB11 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
23VSS1_GND0V electrical ground return terminal (VSS1_) for internal core logic, I/O drivers, and analog sub-blocks.
24VDD1_Power_InPrimary positive power supply input (VDD1_) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
25PB12Digital_IOSignal terminal PB12 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB14Digital_IOSignal terminal PB14 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
28PB15Digital_IOSignal terminal PB15 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
29PA8Digital_IOSignal terminal PA8 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
30PA9Digital_IOSignal terminal PA9 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
31PA10Digital_IOSignal terminal PA10 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
32PA11Digital_IOSignal terminal PA11 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
33PA12Digital_IOSignal terminal PA12 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
34PA13Digital_IOSignal terminal PA13 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
35VSS2_GND0V electrical ground return terminal (VSS2_) for internal core logic, I/O drivers, and analog sub-blocks.
36VDD2_Power_InPrimary positive power supply input (VDD2_) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
37PA14Digital_IOSignal terminal PA14 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
38PA15Digital_IOSignal terminal PA15 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
39PB3Digital_IOSignal terminal PB3 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
40PB4Digital_IOSignal terminal PB4 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
41PB5Digital_IOSignal terminal PB5 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
42PB6Digital_IOSignal terminal PB6 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
43PB7Digital_IOSignal terminal PB7 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 2.7V~5.5V domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
46PB9Digital_IOSignal terminal PB9 (I/O, 2.7V~5.5V domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
47VSS3_GND0V electrical ground return terminal (VSS3_) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD3_Power_InPrimary positive power supply input (VDD3_) operating in the 2.7V~5.5V domain (Max rating: 5.5V).
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