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STM32MP157AAD3T (TFBGA-257) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32MP157AAD3T

STID: C2680171TFBGA-257 · 257 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32MP157AAD3T (TFBGA-257)A1VSSA2PD1A3PB7A4PC6A6VSSA7PD3A9PC8A10PE4A12DSI_CKPA13DSI_D1PA15JTDO - TRACEA16JTCKSWCLK -A17DDR_DQ0A18DDR_DQ1A19VSSB1PG15B2PE6B3PD7B4PA15B5PG6B6PB4B7PE5B8PA8B9PC9B10PC10B11DSI_D0PB12DSI_CKNB13DSI_D1NB14NJTRSTB15JTDIB16DDR_DQ3B17DDR_DQ7B18DDR_DQS0NB19DDR_DQS0PC1PE12C2PE0C3PD4C4PD5C5PD0C6PA9C7PB3C8PB15C9PB9C10PC7C11PC11C12DSI_D0NC13VDD_DSIC14VSSC15JTMS SWDIO -C16DDR_ RESETNC17DDR_DQM0C18DDR_DQ2C19DDR_DQ6D1PG12D2PE11D3PE15D17VSSD18DDR_DQ4D19DDR_DQ5E1PD8E2NRSTE3PE13E17DDR_A13E18DDR_A9F2PC15 - OSC32F3VSSF17DDR_A2F18VSSF19DDR_A3G1VSSG2PC14 - OSC32G3PC13G17VSSG18DDR_A0G19DDR_BA0H1BOOT2H2PH0 OSC IN -H3BOOT0H17DDR_BA2H18DDR_ODTJ2PH1 - OSC_OUJ3NRST_COREJ17DDR_CSNJ18DDR_WENJ19DDR_CASNK1PWR_LPK2PDR_ON_ COREK3BOOT1K17VSSK18DDR_CLKNK19VSSL1PA14L2PA13L3PDR_ONL17DDR_CLKPL18DDR_A15M2PWR_ONM3VREF+M17DDR_A10M18DDR_A12M19DDR_A1N1VSSN2PA3N3PA0N17VSSN18DDR_A14N19DDR_A11P1PE2P2PC2P3PC3P17DDR_CKEP18DDR_BA1R2PG14R3PG13R17DDR_A4R18DDR_DQ8R19VSST1PA1T2PC1T3PA2T17DDR_A8T18DDR_DQ13T19DDR_DQ10U1PB1U2PB0U3PB11U4PC0U5PB10U6PG111J9VSS1J8USB_RREF1J7PF101J6VDDA1V1_ REG1J5VSS1J4PE91J3VDD1J2PB131J1PA41H9VDDQ_DDR1H8VSS1H7VDD3V3_ USB1H6VSS1H5VDDA1V8_ REG1H4VSS1H3VSS1H2VSS1H1PA51G9DDR_A61G8VDDCORE1G7VSS1G6VDDCORE1G5VSS1G4VDD1G3VDD1G2VSS1G1VSSA1F9VDDQ_DDR1F8DDR_ATO1F7VDDCORE1F6VSS1F5VDDCORE1F4VSS1F3VDD1F2VDDA1F1VDDA1E9DDR_RASN1E8VDDCORE1E7VSS1E6VDDCORE1E5VSS1E4VDDCORE1E3VSS1E2VDD1E1PD141D9VDDQ_DDR1D8DDR_DTO01D7VDDCORE1D6VSS1D5VDDCORE1D4VSS1D3VDDCORE1D2VSS1D1VBAT1C9DDR_A51C8DDR_DTO11C7VSS1C6VDDCORE1C5VSS1C4VDDCORE1C3VSS1C2PD151C1PD91B9VDDQ_DDR1B8VSS1B7VDD1V2_DSI_ 1B6VDDA1V8_DSI1B5VDDCORE1B4PC121B3VDDCORE1B2PE141B1PD61A9DDR_A71A8DDR_ZQ1A7VDD1V2_DSI_ 1A6VSS1A5PD21A4PB141A3PE31A2PD101A1PE1W19VSSW18DDR_DQ11W17DDR_DQ12W16DDR_VREFW14USB_DM1W13VSSW11PB6W10USB_DM2W8PG9W7PF7W5VSSW4PF11W3PA6W2PA7W1VSSV19DDR_DQS1PV18DDR_DQM1V17DDR_DQ15V16OTG_VBUSV15PA12V14USB_DP1V13PB2V12PE10V11PG7V10USB_DP2V9PF9V8PF8V7PE7V6PG8V5PB5V4PB8V3PB12V2PC4V1PC5U19DDR_DQ9U18DDR_DQS1NU17DDR_DQ14U16PA10U15PA11U14PD12U13PD13U12PE8U11BYPASS_ REG1U10PF6U9VSSU8PD11U7PG10Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.8170.2165.1160.0154.9149.9144.8139.7134.6129.5124.5119.4114.3109.2104.199.194.088.983.878.773.768.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6-73.7-78.7-83.8-88.9-94.0-99.1-104.1-109.2-114.3-119.4-124.5-129.5-134.6-139.7-144.8-149.9-154.9-160.0-165.1-170.2mm
2. 2D FOOTPRINT
A1A2A3A4A6A7A9A10A12A13A15A16A17A18A19B1B2B3B4B5B6B7B8B9B10B11B12B13B14B15B16B17B18B19C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19D1D2D3D17D18D19E1E2E3E17E18F2F3F17F18F19G1G2G3G17G18G19H1H2H3H17H18J2J3J17J18J19K1K2K3K17K18K19L1L2L3L17L18M2M3M17M18M19N1N2N3N17N18N19P1P2P3P17P18R2R3R17R18R19T1T2T3T17T18T19U1U2U3U4U5U6U7U8U9U10U11U12U13U14U15U16U17U18U19V1V2V3V4V5V6V7V8V9V10V11V12V13V14V15V16V17V18V19W1W2W3W4W5W7W8W10W11W13W14W16W17W18W191A11A21A31A41A51A61A71A81A91B11B21B31B41B51B61B71B81B91C11C21C31C41C51C61C71C81C91D11D21D31D41D51D61D71D81D91E11E21E31E41E51E61E71E81E91F11F21F31F41F51F61F71F81F91G11G21G31G41G51G61G71G81G91H11H21H31H41H51H61H71H81H91J11J21J31J41J51J61J71J81J9E=10.00mm · Pitch e=0.50mmD=10.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (257/257)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSGNDGround Reference Pin (VSS)
A2PD1I/OMultiplexed I/O & Peripheral Pin PD1 (UART, I2C)
A3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
A4PC6I/OMultiplexed I/O & Peripheral Pin PC6 (UART)
A6VSSGNDGround Reference Pin (VSS)
A7PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
A9PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
A10PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
A12DSI_CKPI/OMultiplexed I/O & Peripheral Pin DSI_CKP (General)
A13DSI_D1PI/OMultiplexed I/O & Peripheral Pin DSI_D1P (General)
A15JTDO - TRACESWOI/OMultiplexed I/O & Peripheral Pin JTDO - TRACESWO (SWD/JTAG)
A16JTCKSWCLK -I/OMultiplexed I/O & Peripheral Pin JTCKSWCLK - (SWD/JTAG)
A17DDR_DQ0I/OMultiplexed I/O & Peripheral Pin DDR_DQ0 (General)
A18DDR_DQ1I/OMultiplexed I/O & Peripheral Pin DDR_DQ1 (General)
A19VSSGNDGround Reference Pin (VSS)
B1PG15I/OMultiplexed I/O & Peripheral Pin PG15 (UART, SPI, I2C)
B2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (SPI)
B3PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART, I2C)
B4PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI)
B5PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
B6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
B7PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
B8PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, SPI, I2C, RTC/CLK)
B9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM)
B10PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B11DSI_D0PI/OMultiplexed I/O & Peripheral Pin DSI_D0P (General)
B12DSI_CKNI/OMultiplexed I/O & Peripheral Pin DSI_CKN (General)
B13DSI_D1NI/OMultiplexed I/O & Peripheral Pin DSI_D1N (General)
B14NJTRSTI/OMultiplexed I/O & Peripheral Pin NJTRST (SWD/JTAG)
B15JTDII/OMultiplexed I/O & Peripheral Pin JTDI (SWD/JTAG)
B16DDR_DQ3I/OMultiplexed I/O & Peripheral Pin DDR_DQ3 (General)
B17DDR_DQ7I/OMultiplexed I/O & Peripheral Pin DDR_DQ7 (General)
B18DDR_DQS0NI/OMultiplexed I/O & Peripheral Pin DDR_DQS0N (General)
B19DDR_DQS0PI/OMultiplexed I/O & Peripheral Pin DDR_DQS0P (General)
C1PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI, PWM)
C2PE0I/OMultiplexed I/O & Peripheral Pin PE0 (SPI)
C3PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
C4PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
C5PD0I/OMultiplexed I/O & Peripheral Pin PD0 (UART, I2C)
C6PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, PWM)
C7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (UART, SPI)
C8PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, SPI, RTC/CLK)
C9PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI)
C10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART)
C11PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C12DSI_D0NI/OMultiplexed I/O & Peripheral Pin DSI_D0N (General)
C13VDD_DSIPowerPower Supply Input (VDD_DSI — 3.3V VDD (Max 4.0V))
C14VSSGNDGround Reference Pin (VSS)
C15JTMS SWDIO -I/OMultiplexed I/O & Peripheral Pin JTMS SWDIO - (SWD/JTAG)
C16DDR_ RESETNISystem Enable & Hardware Reset (DDR_ RESETN)
C17DDR_DQM0I/OMultiplexed I/O & Peripheral Pin DDR_DQM0 (General)
C18DDR_DQ2I/OMultiplexed I/O & Peripheral Pin DDR_DQ2 (General)
C19DDR_DQ6I/OMultiplexed I/O & Peripheral Pin DDR_DQ6 (General)
D1PG12I/OMultiplexed I/O & Peripheral Pin PG12 (UART, SPI)
D2PE11I/OMultiplexed I/O & Peripheral Pin PE11 (SPI, PWM)
D3PE15I/OMultiplexed I/O & Peripheral Pin PE15 (UART, SPI)
D17VSSGNDGround Reference Pin (VSS)
D18DDR_DQ4I/OMultiplexed I/O & Peripheral Pin DDR_DQ4 (General)
D19DDR_DQ5I/OMultiplexed I/O & Peripheral Pin DDR_DQ5 (General)
E1PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
E2NRSTISystem Enable & Hardware Reset (NRST)
E3PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
E17DDR_A13I/OMultiplexed I/O & Peripheral Pin DDR_A13 (General)
E18DDR_A9I/OMultiplexed I/O & Peripheral Pin DDR_A9 (General)
F2PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
F3VSSGNDGround Reference Pin (VSS)
F17DDR_A2I/OMultiplexed I/O & Peripheral Pin DDR_A2 (General)
F18VSSGNDGround Reference Pin (VSS)
F19DDR_A3I/OMultiplexed I/O & Peripheral Pin DDR_A3 (General)
G1VSSGNDGround Reference Pin (VSS)
G2PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
G3PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
G17VSSGNDGround Reference Pin (VSS)
G18DDR_A0I/OMultiplexed I/O & Peripheral Pin DDR_A0 (General)
G19DDR_BA0I/OMultiplexed I/O & Peripheral Pin DDR_BA0 (General)
H1BOOT2I/OMultiplexed I/O & Peripheral Pin BOOT2 (General)
H2PH0 OSC IN -_I/OMultiplexed I/O & Peripheral Pin PH0 OSC IN -_ (RTC/CLK)
H3BOOT0IInput-Only Pin BOOT0 (General)
H17DDR_BA2I/OMultiplexed I/O & Peripheral Pin DDR_BA2 (General)
H18DDR_ODTI/OMultiplexed I/O & Peripheral Pin DDR_ODT (General)
J2PH1 - OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OUT (RTC/CLK)
J3NRST_COREI/OMultiplexed I/O & Peripheral Pin NRST_CORE (General)
J17DDR_CSNI/OMultiplexed I/O & Peripheral Pin DDR_CSN (SPI)
J18DDR_WENI/OMultiplexed I/O & Peripheral Pin DDR_WEN (General)
J19DDR_CASNI/OMultiplexed I/O & Peripheral Pin DDR_CASN (General)
K1PWR_LPI/OMultiplexed I/O & Peripheral Pin PWR_LP (General)
K2PDR_ON_ COREI/OMultiplexed I/O & Peripheral Pin PDR_ON_ CORE (General)
K3BOOT1I/OMultiplexed I/O & Peripheral Pin BOOT1 (General)
K17VSSGNDGround Reference Pin (VSS)
K18DDR_CLKNI/OMultiplexed I/O & Peripheral Pin DDR_CLKN (General)
K19VSSGNDGround Reference Pin (VSS)
L1PA14I/OMultiplexed I/O & Peripheral Pin PA14 (RTC/CLK)
L2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (UART, RTC/CLK)
L3PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
L17DDR_CLKPI/OMultiplexed I/O & Peripheral Pin DDR_CLKP (General)
L18DDR_A15I/OMultiplexed I/O & Peripheral Pin DDR_A15 (General)
M2PWR_ONI/OMultiplexed I/O & Peripheral Pin PWR_ON (General)
M3VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
M17DDR_A10I/OMultiplexed I/O & Peripheral Pin DDR_A10 (General)
M18DDR_A12I/OMultiplexed I/O & Peripheral Pin DDR_A12 (General)
M19DDR_A1I/OMultiplexed I/O & Peripheral Pin DDR_A1 (General)
N1VSSGNDGround Reference Pin (VSS)
N2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
N3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
N17VSSGNDGround Reference Pin (VSS)
N18DDR_A14I/OMultiplexed I/O & Peripheral Pin DDR_A14 (General)
N19DDR_A11I/OMultiplexed I/O & Peripheral Pin DDR_A11 (General)
P1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (UART, I2C)
P2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, SPI, ADC)
P3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
P17DDR_CKEI/OMultiplexed I/O & Peripheral Pin DDR_CKE (General)
P18DDR_BA1I/OMultiplexed I/O & Peripheral Pin DDR_BA1 (General)
R2PG14I/OMultiplexed I/O & Peripheral Pin PG14 (UART, SPI)
R3PG13I/OMultiplexed I/O & Peripheral Pin PG13 (UART, SPI)
R17DDR_A4I/OMultiplexed I/O & Peripheral Pin DDR_A4 (General)
R18DDR_DQ8I/OMultiplexed I/O & Peripheral Pin DDR_DQ8 (General)
R19VSSGNDGround Reference Pin (VSS)
T1PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
T2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
T3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
T17DDR_A8I/OMultiplexed I/O & Peripheral Pin DDR_A8 (General)
T18DDR_DQ13I/OMultiplexed I/O & Peripheral Pin DDR_DQ13 (General)
T19DDR_DQ10I/OMultiplexed I/O & Peripheral Pin DDR_DQ10 (General)
U1PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
U2PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
U3PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C, PWM)
U4PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
U5PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C, PWM)
U6PG11I/OMultiplexed I/O & Peripheral Pin PG11 (UART)
U7PG10I/OMultiplexed I/O & Peripheral Pin PG10 (UART)
U8PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C)
U9VSSGNDGround Reference Pin (VSS)
U10PF6I/OMultiplexed I/O & Peripheral Pin PF6 (SPI)
U11BYPASS_ REG1V8I/OMultiplexed I/O & Peripheral Pin BYPASS_ REG1V8 (General)
U12PE8I/OMultiplexed I/O & Peripheral Pin PE8 (UART, PWM)
U13PD13I/OMultiplexed I/O & Peripheral Pin PD13 (SPI, I2C)
U14PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, I2C)
U15PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, I2C, PWM)
U16PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, SPI)
U17DDR_DQ14I/OMultiplexed I/O & Peripheral Pin DDR_DQ14 (General)
U18DDR_DQS1NI/OMultiplexed I/O & Peripheral Pin DDR_DQS1N (General)
U19DDR_DQ9I/OMultiplexed I/O & Peripheral Pin DDR_DQ9 (General)
V1PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
V2PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
V3PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
V4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART)
V5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM)
V6PG8I/OMultiplexed I/O & Peripheral Pin PG8 (UART, SPI)
V7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
V8PF8I/OMultiplexed I/O & Peripheral Pin PF8 (UART, SPI)
V9PF9I/OMultiplexed I/O & Peripheral Pin PF9 (UART, SPI)
V10USB_DP2I/OMultiplexed I/O & Peripheral Pin USB_DP2 (USB)
V11PG7I/OMultiplexed I/O & Peripheral Pin PG7 (UART)
V12PE10I/OMultiplexed I/O & Peripheral Pin PE10 (UART, PWM)
V13PB2I/OMultiplexed I/O & Peripheral Pin PB2 (UART, SPI, I2C, RTC/CLK)
V14USB_DP1I/OMultiplexed I/O & Peripheral Pin USB_DP1 (USB)
V15PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, I2C)
V16OTG_VBUSPowerPower Supply Input (OTG_VBUS — 3.3V VDD (5V-Tolerant FT))
V17DDR_DQ15I/OMultiplexed I/O & Peripheral Pin DDR_DQ15 (General)
V18DDR_DQM1I/OMultiplexed I/O & Peripheral Pin DDR_DQM1 (General)
V19DDR_DQS1PI/OMultiplexed I/O & Peripheral Pin DDR_DQS1P (General)
W1VSSGNDGround Reference Pin (VSS)
W2PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC, PWM)
W3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
W4PF11I/OMultiplexed I/O & Peripheral Pin PF11 (SPI, ADC)
W5VSSGNDGround Reference Pin (VSS)
W7PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
W8PG9I/OMultiplexed I/O & Peripheral Pin PG9 (UART)
W10USB_DM2I/OMultiplexed I/O & Peripheral Pin USB_DM2 (USB)
W11PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
W13VSSGNDGround Reference Pin (VSS)
W14USB_DM1I/OMultiplexed I/O & Peripheral Pin USB_DM1 (USB)
W16DDR_VREFAnalogMultiplexed I/O & Peripheral Pin DDR_VREF (General)
W17DDR_DQ12I/OMultiplexed I/O & Peripheral Pin DDR_DQ12 (General)
W18DDR_DQ11I/OMultiplexed I/O & Peripheral Pin DDR_DQ11 (General)
W19VSSGNDGround Reference Pin (VSS)
1A1PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
1A2PD10I/OMultiplexed I/O & Peripheral Pin PD10 (SPI, RTC/CLK)
1A3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
1A4PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
1A5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
1A6VSSGNDGround Reference Pin (VSS)
1A7VDD1V2_DSI_ REGPowerPower Supply Input (VDD1V2_DSI_ REG — 3.3V VDD (Max 4.0V))
1A8DDR_ZQI/OMultiplexed I/O & Peripheral Pin DDR_ZQ (General)
1A9DDR_A7I/OMultiplexed I/O & Peripheral Pin DDR_A7 (General)
1B1PD6I/OMultiplexed I/O & Peripheral Pin PD6 (SPI)
1B2PE14I/OMultiplexed I/O & Peripheral Pin PE14 (UART, PWM)
1B3VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1B4PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI, RTC/CLK)
1B5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1B6VDDA1V8_DSIPowerPower Supply Input (VDDA1V8_DSI — 3.3V VDD (Max 4.0V))
1B7VDD1V2_DSI_ PHYPowerPower Supply Input (VDD1V2_DSI_ PHY — 3.3V VDD (Max 4.0V))
1B8VSSGNDGround Reference Pin (VSS)
1B9VDDQ_DDRPowerPower Supply Input (VDDQ_DDR — 3.3V VDD (Max 4.0V))
1C1PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
1C2PD15I/OMultiplexed I/O & Peripheral Pin PD15 (UART)
1C3VSSGNDGround Reference Pin (VSS)
1C4VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1C5VSSGNDGround Reference Pin (VSS)
1C6VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1C7VSSGNDGround Reference Pin (VSS)
1C8DDR_DTO1I/OMultiplexed I/O & Peripheral Pin DDR_DTO1 (General)
1C9DDR_A5I/OMultiplexed I/O & Peripheral Pin DDR_A5 (General)
1D1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
1D2VSSGNDGround Reference Pin (VSS)
1D3VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1D4VSSGNDGround Reference Pin (VSS)
1D5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1D6VSSGNDGround Reference Pin (VSS)
1D7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1D8DDR_DTO0I/OMultiplexed I/O & Peripheral Pin DDR_DTO0 (General)
1D9VDDQ_DDRPowerPower Supply Input (VDDQ_DDR — 3.3V VDD (Max 4.0V))
1E1PD14I/OMultiplexed I/O & Peripheral Pin PD14 (UART)
1E2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
1E3VSSGNDGround Reference Pin (VSS)
1E4VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1E5VSSGNDGround Reference Pin (VSS)
1E6VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1E7VSSGNDGround Reference Pin (VSS)
1E8VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1E9DDR_RASNI/OMultiplexed I/O & Peripheral Pin DDR_RASN (General)
1F1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
1F2VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
1F3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
1F4VSSGNDGround Reference Pin (VSS)
1F5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1F6VSSGNDGround Reference Pin (VSS)
1F7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1F8DDR_ATOI/OMultiplexed I/O & Peripheral Pin DDR_ATO (General)
1F9VDDQ_DDRPowerPower Supply Input (VDDQ_DDR — 3.3V VDD (Max 4.0V))
1G1VSSAGNDGround Reference Pin (VSSA)
1G2VSSGNDGround Reference Pin (VSS)
1G3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
1G4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
1G5VSSGNDGround Reference Pin (VSS)
1G6VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1G7VSSGNDGround Reference Pin (VSS)
1G8VDDCOREPowerPower Supply Input (VDDCORE — 3.3V VDD (Max 4.0V))
1G9DDR_A6I/OMultiplexed I/O & Peripheral Pin DDR_A6 (General)
1H1PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
1H2VSSGNDGround Reference Pin (VSS)
1H3VSSGNDGround Reference Pin (VSS)
1H4VSSGNDGround Reference Pin (VSS)
1H5VDDA1V8_ REGPowerPower Supply Input (VDDA1V8_ REG — 3.3V VDD (Max 4.0V))
1H6VSSGNDGround Reference Pin (VSS)
1H7VDD3V3_ USBPowerPower Supply Input (VDD3V3_ USB — 3.3V VDD (Max 4.0V))
1H8VSSGNDGround Reference Pin (VSS)
1H9VDDQ_DDRPowerPower Supply Input (VDDQ_DDR — 3.3V VDD (Max 4.0V))
1J1PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
1J2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
1J3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
1J4PE9I/OMultiplexed I/O & Peripheral Pin PE9 (UART, PWM)
1J5VSSGNDGround Reference Pin (VSS)
1J6VDDA1V1_ REGPowerPower Supply Input (VDDA1V1_ REG — 3.3V VDD (Max 4.0V))
1J7PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
1J8USB_RREFI/OMultiplexed I/O & Peripheral Pin USB_RREF (USB)
1J9VSSGNDGround Reference Pin (VSS)
PIN A1 VSS
GND
Ground Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32MP157AAD3T (ST · TFBGA-257)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32MP157AAD3T (TFBGA-257) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32MP157AAD3T (TFBGA-257) - 2. Standard Pinout (Top View)
True package pinout (257 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32MP157AAD3T (TFBGA-257) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32MP157AAD3T (TFBGA-257) - 4. Package Dimensions (D×E×A)
TFBGA-257 · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32MP157AAD3T (TFBGA-257) - 5. Recommended Land Pattern
IPC-7351B Footprint (257 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32MP157AAD3T (TFBGA-257) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for STM32MP157
P59 · p59_fig01EXACT PACKAGE
STM32MP157AAD3T (TFBGA-257) — Figure 5. STM32MP157A/DADxx TFBGA257 pinout
Figure 5. STM32MP157A/DADxx TFBGA257 pinout
P242 · p242_fig01EXACT PACKAGE
STM32MP157AAD3T (TFBGA-257) — Figure 67. TFBGA257 - Recommended footprint
Figure 67. TFBGA257 - Recommended footprint
P1 · p01_fig01881×439px
STM32MP157AAD3T (TFBGA-257) — • 32-bit dual-core Arm® Cortex®-A7 - L1 32-Kbyte I / 32-Kbyte D for each core - 256-Kbyte unified level 2 cache - Arm® NEON™ and Arm® TrustZone®
• 32-bit dual-core Arm® Cortex®-A7 - L1 32-Kbyte I / 32-Kbyte D for each core - 256-Kbyte unified level 2 cache - Arm® NEON™ and Arm® TrustZone®
P59 · p59_fig01P59
STM32MP157AAD3T (TFBGA-257) — Datasheet Page 59 (p59_fig01)
Datasheet Page 59 (p59_fig01)
P61 · p61_fig011751×1814px
STM32MP157AAD3T (TFBGA-257) — Figure 7. STM32MP157A/DACxx TFBGA361 pinout
Figure 7. STM32MP157A/DACxx TFBGA361 pinout
P123 · p123_fig011751×2074px
STM32MP157AAD3T (TFBGA-257) — Figure 11. Power supply scheme
Figure 11. Power supply scheme
P123 · p123_fig01P123
STM32MP157AAD3T (TFBGA-257) — Datasheet Page 123 (p123_fig01)
Datasheet Page 123 (p123_fig01)
P152 · p152_fig011546×498px
STM32MP157AAD3T (TFBGA-257) — Figure 19. Typical application with a 24 MHz crystal fHSE CL1
Figure 19. Typical application with a 24 MHz crystal fHSE CL1
P153 · p153_fig011546×497px
STM32MP157AAD3T (TFBGA-257) — Figure 20. Typical application with a 32.768 kHz crystal fHSE CL1
Figure 20. Typical application with a 32.768 kHz crystal fHSE CL1
P245 · p245_fig011553×716px
STM32MP157AAD3T (TFBGA-257) — Figure 70. LFBGA354 - Recommended footprint
Figure 70. LFBGA354 - Recommended footprint
P246 · p246_fig011546×1018px
STM32MP157AAD3T (TFBGA-257) — Figure 71. LFBGA354 marking (package top view)
Figure 71. LFBGA354 marking (package top view)
P246 · p246_fig01P246
STM32MP157AAD3T (TFBGA-257) — Datasheet Page 246 (p246_fig01)
Datasheet Page 246 (p246_fig01)

Technical Specifications & Part Details (STM32MP157AAD3T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32MP157AAD3T (TFBGA-257) is a 257-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
800 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
114 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.25 mm)
Package family: BGA (TFBGA-257)
Pin Count & Lead PitchN / e
257 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, BOOT1): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol257 auto-grouped pins
OK
IPC-7351B Land Pattern257 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-257)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.24 × 0.24 mm
Pins / Total PadsTopology
257P / 257Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-257
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32MP157AAD3T (TFBGA-257)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32MP157AAD3T (TFBGA-257)?

Manufactured by ST, the STM32MP157AAD3T is housed in a TFBGA-257 package with 257 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (PD1: Multiplexed I/O & Peripheral Pin PD1 (UART, I2C)), A3 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)), A4 (PC6: Multiplexed I/O & Peripheral Pin PC6 (UART)), A6 (VSS: Ground Reference Pin (VSS)), A7 (PD3: Multiplexed I/O & Peripheral Pin PD3 (UART, SPI)).

What are the IPC-7351B PCB Footprint dimensions for STM32MP157AAD3T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32MP157AAD3T (TFBGA-257) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 257 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32MP157AAD3T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32MP157AAD3T (ST, TFBGA-257) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (257 pins) & STM32MP157 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A2PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART, I2C.
A3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C.
A4PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART.
A6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A7PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
A9PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
A10PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS_SAI1FSA. Supported peripheral buses: SPI.
A12DSI_CKPDigital_IOSignal terminal DSI_CKP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_CKP. Supported peripheral buses: General.
A13DSI_D1PDigital_IOSignal terminal DSI_D1P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D1P. Supported peripheral buses: General.
A15JTDO - TRACESWODigital_IOSignal terminal JTDO - TRACESWO (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDO - TRACESWO. Supported peripheral buses: SWD/JTAG.
A16JTCKSWCLK -Digital_IOSignal terminal JTCKSWCLK - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTCKSWCLK -. Supported peripheral buses: SWD/JTAG.
A17DDR_DQ0Digital_IOSignal terminal DDR_DQ0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ0. Supported peripheral buses: General.
A18DDR_DQ1Digital_IOSignal terminal DDR_DQ1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ1. Supported peripheral buses: General.
A19VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1PG15Digital_IOSignal terminal PG15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, SPI, I2C.
B2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI_SAI1SDA. Supported peripheral buses: SPI.
B3PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART, I2C.
B4PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI.
B5PG6Digital_IOSignal terminal PG6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG6. Supported peripheral buses: General.
B6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO, SPI2_NSS, SPI6_MISOSDMMC2D3. Supported peripheral buses: SPI, PWM.
B7PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO_SAI1SCKA. Supported peripheral buses: SPI.
B8PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C, RTC/CLK.
B9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM.
B10PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B11DSI_D0PDigital_IOSignal terminal DSI_D0P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D0P. Supported peripheral buses: General.
B12DSI_CKNDigital_IOSignal terminal DSI_CKN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_CKN. Supported peripheral buses: General.
B13DSI_D1NDigital_IOSignal terminal DSI_D1N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D1N. Supported peripheral buses: General.
B14NJTRSTDigital_IOSignal terminal NJTRST (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: NJTRST. Supported peripheral buses: SWD/JTAG.
B15JTDIDigital_IOSignal terminal JTDI (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTDI. Supported peripheral buses: SWD/JTAG.
B16DDR_DQ3Digital_IOSignal terminal DDR_DQ3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ3. Supported peripheral buses: General.
B17DDR_DQ7Digital_IOSignal terminal DDR_DQ7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ7. Supported peripheral buses: General.
B18DDR_DQS0NDigital_IOSignal terminal DDR_DQS0N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQS0N. Supported peripheral buses: General.
B19DDR_DQS0PDigital_IOSignal terminal DDR_DQS0P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQS0P. Supported peripheral buses: General.
C1PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCKSDMMC1D0DIR. Supported peripheral buses: SPI, PWM.
C2PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI.
C3PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART.
C4PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
C5PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: UART, I2C.
C6PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
C7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: UART, SPI.
C8PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI, RTC/CLK.
C9PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
C10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: UART.
C11PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
C12DSI_D0NDigital_IOSignal terminal DSI_D0N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D0N. Supported peripheral buses: General.
C13VDD_DSIPower_InPrimary positive power supply input (VDD_DSI) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C14VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C15JTMS SWDIO -Digital_IOSignal terminal JTMS SWDIO - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: JTMS SWDIO -. Supported peripheral buses: SWD/JTAG.
C16DDR_ RESETNDigital_IOActive-low hardware reset terminal (DDR_ RESETN): pulling this pin Low resets the processor core and peripherals.
C17DDR_DQM0Digital_IOSignal terminal DDR_DQM0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQM0. Supported peripheral buses: General.
C18DDR_DQ2Digital_IOSignal terminal DDR_DQ2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ2. Supported peripheral buses: General.
C19DDR_DQ6Digital_IOSignal terminal DDR_DQ6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ6. Supported peripheral buses: General.
D1PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: UART, SPI.
D2PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSSUSART6CK. Supported peripheral buses: SPI, PWM.
D3PE15Digital_IOSignal terminal PE15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE15. Supported peripheral buses: UART, SPI.
D17VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D18DDR_DQ4Digital_IOSignal terminal DDR_DQ4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ4. Supported peripheral buses: General.
D19DDR_DQ5Digital_IOSignal terminal DDR_DQ5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_DQ5. Supported peripheral buses: General.
E1PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART.
E2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E3PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
E17DDR_A13Digital_IOSignal terminal DDR_A13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_A13. Supported peripheral buses: General.
E18DDR_A9Digital_IOSignal terminal DDR_A9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DDR_A9. Supported peripheral buses: General.
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