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LE89810BSCT (SOIC-16-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

LE89810BSCT

MICROCHIPID: C2651980SOIC-16-300mil · 16 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LE89810BSCT (SOIC-16-300mil)1TIP2VBAT3BGND4VCC5RSN6LSN7VREF8IBI16RING15RSVD14RSVD13AGND12RSVD11IBR10IBT9TFLTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=7.50mm · Pitch e=1.27mmD=10.30mm-8-6-4-20246886420-2-4-6-8mm
3. 3D CAD MODEL
Package Body: 7.50mm × 10.30mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1TIPI/OMultiplexed I/O & Peripheral Pin TIP (General)
2VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
3BGNDGNDGround Reference Pin (BGND)
4VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
5RSNI/OMultiplexed I/O & Peripheral Pin RSN (General)
6LSNI/OMultiplexed I/O & Peripheral Pin LSN (General)
7VREFI/OMultiplexed I/O & Peripheral Pin VREF (General)
8IBII/OMultiplexed I/O & Peripheral Pin IBI (General)
9TFLTI/OMultiplexed I/O & Peripheral Pin TFLT (General)
10IBTI/OMultiplexed I/O & Peripheral Pin IBT (General)
11IBRI/OMultiplexed I/O & Peripheral Pin IBR (General)
12RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
13AGNDGNDGround Reference Pin (AGND)
14RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
15RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
16RINGI/OMultiplexed I/O & Peripheral Pin RING (General)
PIN 1 TIP
I/O
Multiplexed I/O & Peripheral Pin TIP (General)
Design note: Signal terminal TIP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TIP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LE89810BSCT (MICROCHIP · SOIC-16-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LE89810BSCT (SOIC-16-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LE89810BSCT (SOIC-16-300mil) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LE89810BSCT (SOIC-16-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LE89810BSCT (SOIC-16-300mil) - 4. Package Dimensions (D×E×A)
SOIC-16-300mil · 7.50×10.30mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
LE89810BSCT (SOIC-16-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
LE89810BSCT (SOIC-16-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (LE89810BSCT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LE89810BSCT (SOIC-16-300mil) is a 16-pin standard electronic & interconnect component featuring a 10.30 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.30 × 7.50 × 2.70 mm (A1=0.20 mm)
Package family: SOIC (SOIC-16-300mil)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-16-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.30 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-16-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LE89810BSCT (SOIC-16-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LE89810BSCT (SOIC-16-300mil)?

Manufactured by MICROCHIP, the LE89810BSCT is housed in a SOIC-16-300mil package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (TIP: Multiplexed I/O & Peripheral Pin TIP (General)), 2 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 3 (BGND: Ground Reference Pin (BGND)), 4 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 5 (RSN: Multiplexed I/O & Peripheral Pin RSN (General)), 6 (LSN: Multiplexed I/O & Peripheral Pin LSN (General)).

What are the IPC-7351B PCB Footprint dimensions for LE89810BSCT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LE89810BSCT (SOIC-16-300mil) has a nominal body envelope of 7.50 × 10.30 mm, pitch e = 1.27 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LE89810BSCT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LE89810BSCT (MICROCHIP, SOIC-16-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & LE89810 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1TIPDigital_IOSignal terminal TIP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TIP. Supported peripheral buses: General.
2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3BGNDGND0V electrical ground return terminal (BGND) for internal core logic, I/O drivers, and analog sub-blocks.
4VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
5RSNDigital_IOSignal terminal RSN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSN. Supported peripheral buses: General.
6LSNDigital_IOSignal terminal LSN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LSN. Supported peripheral buses: General.
7VREFDigital_IOSignal terminal VREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
8IBIDigital_IOSignal terminal IBI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IBI. Supported peripheral buses: General.
9TFLTDigital_IOSignal terminal TFLT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TFLT. Supported peripheral buses: General.
10IBTDigital_IOSignal terminal IBT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IBT. Supported peripheral buses: General.
11IBRDigital_IOSignal terminal IBR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IBR. Supported peripheral buses: General.
12RSVDDigital_IOSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
13AGNDGND0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
14RSVDDigital_IOSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
15RSVDDigital_IOSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
16RINGDigital_IOSignal terminal RING (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RING. Supported peripheral buses: General.
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