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VSC8115XYA-05-T (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

VSC8115XYA-05-T

MICROCHIPID: C2651437TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · VSC8115XYA-05-T (TSSOP-20)1VDDA2DATAIN+3DATAIN-4VSSA5LOCKDET6STS127REFCLK8LOCKREFN9VSS10VDD20VDDA19VSSA18CAP+17CAP-16BYPASS15SD14DATAOUT+13DATAOUT-12CLKOUT+11CLKOUT-Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
2DATAIN+I/OMultiplexed I/O & Peripheral Pin DATAIN+ (General)
3DATAIN-I/OMultiplexed I/O & Peripheral Pin DATAIN- (General)
4VSSAGNDGround Reference Pin (VSSA)
5LOCKDETI/OMultiplexed I/O & Peripheral Pin LOCKDET (General)
6STS12I/OMultiplexed I/O & Peripheral Pin STS12 (General)
7REFCLKI/OMultiplexed I/O & Peripheral Pin REFCLK (General)
8LOCKREFNI/OMultiplexed I/O & Peripheral Pin LOCKREFN (General)
9VSSGNDGround Reference Pin (VSS)
10VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
11CLKOUT-I/OMultiplexed I/O & Peripheral Pin CLKOUT- (General)
12CLKOUT+I/OMultiplexed I/O & Peripheral Pin CLKOUT+ (General)
13DATAOUT-I/OMultiplexed I/O & Peripheral Pin DATAOUT- (General)
14DATAOUT+I/OMultiplexed I/O & Peripheral Pin DATAOUT+ (General)
15SDI/OMultiplexed I/O & Peripheral Pin SD (General)
16BYPASSI/OMultiplexed I/O & Peripheral Pin BYPASS (General)
17CAP-I/OMultiplexed I/O & Peripheral Pin CAP- (General)
18CAP+I/OMultiplexed I/O & Peripheral Pin CAP+ (General)
19VSSAGNDGround Reference Pin (VSSA)
20VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
PIN 1 VDDA
Power
Power Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: VSC8115XYA-05-T (MICROCHIP · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
VSC8115XYA-05-T (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
VSC8115XYA-05-T (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
VSC8115XYA-05-T (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
VSC8115XYA-05-T (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
VSC8115XYA-05-T (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
VSC8115XYA-05-T (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (VSC8115XYA-05-T)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:VSC8115XYA-05-T (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — VSC8115XYA-05-T (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of VSC8115XYA-05-T (TSSOP-20)?

Manufactured by MICROCHIP, the VSC8115XYA-05-T is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (VDDA: Power Supply Input (VDDA — 3.3V / 5.0V Standard Logic)), 2 (DATAIN+: Multiplexed I/O & Peripheral Pin DATAIN+ (General)), 3 (DATAIN-: Multiplexed I/O & Peripheral Pin DATAIN- (General)), 4 (VSSA: Ground Reference Pin (VSSA)), 5 (LOCKDET: Multiplexed I/O & Peripheral Pin LOCKDET (General)), 6 (STS12: Multiplexed I/O & Peripheral Pin STS12 (General)).

What are the IPC-7351B PCB Footprint dimensions for VSC8115XYA-05-T?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), VSC8115XYA-05-T (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for VSC8115XYA-05-T?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for VSC8115XYA-05-T (MICROCHIP, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & VSC8115 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2DATAIN+Digital_IOSignal terminal DATAIN+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAIN+. Supported peripheral buses: General.
3DATAIN-Digital_IOSignal terminal DATAIN- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAIN-. Supported peripheral buses: General.
4VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
5LOCKDETDigital_IOSignal terminal LOCKDET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOCKDET. Supported peripheral buses: General.
6STS12Digital_IOSignal terminal STS12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STS12. Supported peripheral buses: General.
7REFCLKDigital_IOSignal terminal REFCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: REFCLK. Supported peripheral buses: General.
8LOCKREFNDigital_IOSignal terminal LOCKREFN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOCKREFN. Supported peripheral buses: General.
9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
10VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11CLKOUT-Digital_IOSignal terminal CLKOUT- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKOUT-. Supported peripheral buses: General.
12CLKOUT+Digital_IOSignal terminal CLKOUT+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLKOUT+. Supported peripheral buses: General.
13DATAOUT-Digital_IOSignal terminal DATAOUT- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAOUT-. Supported peripheral buses: General.
14DATAOUT+Digital_IOSignal terminal DATAOUT+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAOUT+. Supported peripheral buses: General.
15SDDigital_IOSignal terminal SD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD. Supported peripheral buses: General.
16BYPASSDigital_IOSignal terminal BYPASS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BYPASS. Supported peripheral buses: General.
17CAP-Digital_IOSignal terminal CAP- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CAP-. Supported peripheral buses: General.
18CAP+Digital_IOSignal terminal CAP+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CAP+. Supported peripheral buses: General.
19VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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