![STM32U073MCT6 (LQFP-80(12x12)) — Figure 3. UFQFPN32 pinout PF3-BOOT0 32 1 2 UFQFPN32 [UFQFPN-32(5x5)]](/api/v1/assets/C23679798/extracted/figures/p27_fig01.png)
UFQFPN-32(5x5) · 33P
Synchronized Pinout (Symbol / 2D / 3D) (80/80)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VSS | GND | Ground Reference Pin (VSS) |
| 2 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 3 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| 4 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 5 | PC14-OSC32IN | I/O | Multiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK) |
| 6 | PC15-OSC32_OUT | I/O | Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK) |
| 7 | PF0-OSC_IN | I/O | Multiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK) |
| 8 | PF1-OSC_OUT | I/O | Multiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK) |
| 9 | PF2-NRST | I/O | Multiplexed I/O & Peripheral Pin PF2-NRST (General) |
| 10 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (General) |
| 11 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (General) |
| 12 | PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 (General) |
| 13 | PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 (General) |
| 14 | VSSA/VREF- | GND | Ground Reference Pin (VSSA/VREF-) |
| 15 | VREF+ | Analog | Multiplexed I/O & Peripheral Pin VREF+ (General) |
| 16 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 17 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (General) |
| 18 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (General) |
| 19 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (General) |
| 20 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (General) |
| 21 | VSS | GND | Ground Reference Pin (VSS) |
| 22 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 23 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (General) |
| 24 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (General) |
| 25 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (General) |
| 26 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (General) |
| 27 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (General) |
| 28 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (General) |
| 29 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| 30 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| 31 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| 32 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| 33 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (General) |
| 34 | PE9 | I/O | Multiplexed I/O & Peripheral Pin PE9 (General) |
| 35 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (General) |
| 36 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (General) |
| 37 | VSS | GND | Ground Reference Pin (VSS) |
| 38 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 39 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (General) |
| 40 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (General) |
| 41 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (General) |
| 42 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (General) |
| 43 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (General) |
| 44 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (General) |
| 45 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (General) |
| 46 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (General) |
| 47 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (General) |
| 48 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (General) |
| 49 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (General) |
| 50 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| 51 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (General) |
| 52 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (General) |
| 53 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 54 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 55 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 56 | PA11[PA9] | I/O | Multiplexed I/O & Peripheral Pin PA11[PA9] (General) |
| 57 | PA12[PA10] | I/O | Multiplexed I/O & Peripheral Pin PA12[PA10] (General) |
| 58 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| 59 | VSS | GND | Ground Reference Pin (VSS) |
| 60 | VDDUSB | Power | Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V)) |
| 61 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| 62 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| 63 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (General) |
| 64 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (General) |
| 65 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (General) |
| 66 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (General) |
| 67 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (General) |
| 68 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (General) |
| 69 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (General) |
| 70 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (General) |
| 71 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (General) |
| 72 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (General) |
| 73 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 74 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 75 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 76 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| 77 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 78 | PF3-BOOT0 | I/O | Multiplexed I/O & Peripheral Pin PF3-BOOT0 (General) |
| 79 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 80 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
PIN 1 VSS
GNDGround Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 23 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (80 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-80(12x12) · 12.00×12.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (80 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (23 figures · Page 1/2)
Showing 1–12 of 23 uncropped original figures for STM32U073
P1 · p01_fig01EXACT PACKAGE
P30 · p30_fig01EXACT PACKAGE
P128 · p128_fig01EXACT PACKAGE
P130 · p130_fig01EXACT PACKAGE
P1 · p01_fig021408×551px
P30 · p30_fig021065×680px
P42 · p42_fig011278×1130px
P72 · p72_fig011432×512px
P93 · p93_fig01908×757px
P93 · p93_fig021603×614px
P127 · p127_fig01All Packages in PDF
P27 · p27_fig01EXACT PACKAGE
Page 1 / 2 (23 extracted figures)
Technical Specifications & Part Details (STM32U073MCT6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32U073MCT6 (LQFP-80(12x12)) is a 80-pin embedded microcontroller unit (mcu) featuring a 12.00 × 12.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
2 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
12.00 × 12.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-80(12x12))
Pin Count & Lead PitchN / e
80 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PF3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol80 auto-grouped pins
IPC-7351B Land Pattern80 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32U073 (5)
LQFP-48(7x7) · 48P
LQFP-64(10x10) · 64P
LQFP-80(12x12) · 80P
UFBGA-81(5x5) · 81P
Mechanical Dimensions & Land Pattern (LQFP-80(12x12))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
12.00 × 12.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
80P / 80Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-80(12x12) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32U073MCT6 (LQFP-80(12x12))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32U073MCT6 (LQFP-80(12x12))?
Manufactured by ST, the STM32U073MCT6 is housed in a LQFP-80(12x12) package with 80 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VSS: Ground Reference Pin (VSS)), 2 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 3 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 4 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 5 (PC14-OSC32IN: Multiplexed I/O & Peripheral Pin PC14-OSC32IN (RTC/CLK)), 6 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32U073MCT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U073MCT6 (LQFP-80(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.50 mm, and 80 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U073MCT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U073MCT6 (ST, LQFP-80(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (80 pins) & STM32U073 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 2 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 3 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 4 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 5 | PC14-OSC32IN | Digital_IO | Signal terminal PC14-OSC32IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14-OSC32IN. Supported peripheral buses: RTC/CLK. |
| 6 | PC15-OSC32_OUT | Digital_IO | Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| 7 | PF0-OSC_IN | Digital_IO | Signal terminal PF0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN. Supported peripheral buses: RTC/CLK. |
| 8 | PF1-OSC_OUT | Digital_IO | Signal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 9 | PF2-NRST | Digital_IO | Signal terminal PF2-NRST (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2-NRST. Supported peripheral buses: General. |
| 10 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General. |
| 11 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General. |
| 12 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General. |
| 13 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General. |
| 14 | VSSA/VREF- | GND | 0V electrical ground return terminal (VSSA/VREF-) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 16 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 17 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General. |
| 18 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General. |
| 19 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General. |
| 20 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| 21 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 22 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 23 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |
| 24 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| 25 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General. |
| 26 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General. |
| 27 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General. |
| 28 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General. |
| 29 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| 30 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| 31 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| 32 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| 33 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General. |
| 34 | PE9 | Digital_IO | Signal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General. |
| 35 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General. |
| 36 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General. |
| 37 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 38 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 39 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General. |
| 40 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General. |
| 41 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General. |
| 42 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General. |
| 43 | PD8 | Digital_IO | Signal terminal PD8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General. |
| 44 | PD9 | Digital_IO | Signal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General. |
| 45 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General. |
| 46 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General. |
| 47 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General. |
| 48 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General. |
| 49 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General. |
| 50 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |
| 51 | PC8 | Digital_IO | Signal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General. |
| 52 | PC9 | Digital_IO | Signal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General. |
| 53 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General. |
| 54 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General. |
| 55 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 56 | PA11[PA9] | Digital_IO | Signal terminal PA11[PA9] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11[PA9]. Supported peripheral buses: General. |
| 57 | PA12[PA10] | Digital_IO | Signal terminal PA12[PA10] (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12[PA10]. Supported peripheral buses: General. |
| 58 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General. |
| 59 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 60 | VDDUSB | Power_In | Primary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 61 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General. |
| 62 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General. |
| 63 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General. |
| 64 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General. |