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A3PN010-2QNG48 (QFN-48-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

A3PN010-2QNG48

MICROCHIPID: C2616505QFN-48-EP(6x6) · 49 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · A3PN010-2QNG48 (QFN-48-EP(6x6))1GEC0/IO37RSB2IO36RSB13GEA0/IO34RSB4IO22RSB15GND6VCCIB17IO24RSB18IO33RSB19IO26RSB110IO32RSB111IO27RSB112IO29RSB113IO30RSB114IO31RSB115IO28RSB116IO25RSB117IO23RSB118VCC19VCCIB120Revision4 (A21IO14RSB122TCK23TDI24TMS25VPUMP49EP48IO21RSB147IO20RSB146IO19RSB145IO18RSB144IO16RSB143IO15RSB142IO13RSB141IO12RSB140GDC0/IO01RSB39IO03RSB038GDA0/IO05RSB37IO06RSB036IO07RSB035VCC34GND33VCCIB032IO08RSB031IO09RSB030IO10RSB029IO11RSB028VJTAG27TRST26TDOGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.838.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=6.00mm · Pitch e=0.40mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GEC0/IO37RSB1I/OMultiplexed I/O & Peripheral Pin GEC0/IO37RSB1 (General)
2IO36RSB1I/OMultiplexed I/O & Peripheral Pin IO36RSB1 (General)
3GEA0/IO34RSB1I/OMultiplexed I/O & Peripheral Pin GEA0/IO34RSB1 (General)
4IO22RSB1I/OMultiplexed I/O & Peripheral Pin IO22RSB1 (General)
5GNDGNDGround Reference Pin (GND)
6VCCIB1PowerPower Supply Input (VCCIB1 — 3.3V / 5.0V Standard Logic)
7IO24RSB1I/OMultiplexed I/O & Peripheral Pin IO24RSB1 (General)
8IO33RSB1I/OMultiplexed I/O & Peripheral Pin IO33RSB1 (General)
9IO26RSB1I/OMultiplexed I/O & Peripheral Pin IO26RSB1 (General)
10IO32RSB1I/OMultiplexed I/O & Peripheral Pin IO32RSB1 (General)
11IO27RSB1I/OMultiplexed I/O & Peripheral Pin IO27RSB1 (General)
12IO29RSB1I/OMultiplexed I/O & Peripheral Pin IO29RSB1 (General)
13IO30RSB1I/OMultiplexed I/O & Peripheral Pin IO30RSB1 (General)
14IO31RSB1I/OMultiplexed I/O & Peripheral Pin IO31RSB1 (General)
15IO28RSB1I/OMultiplexed I/O & Peripheral Pin IO28RSB1 (General)
16IO25RSB1I/OMultiplexed I/O & Peripheral Pin IO25RSB1 (General)
17IO23RSB1I/OMultiplexed I/O & Peripheral Pin IO23RSB1 (General)
18VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
19VCCIB1PowerPower Supply Input (VCCIB1 — 3.3V / 5.0V Standard Logic)
20Revision4 (August2012)I/OMultiplexed I/O & Peripheral Pin Revision4 (August2012) (General)
21IO14RSB1I/OMultiplexed I/O & Peripheral Pin IO14RSB1 (General)
22TCKI/OMultiplexed I/O & Peripheral Pin TCK (General)
23TDII/OMultiplexed I/O & Peripheral Pin TDI (General)
24TMSI/OMultiplexed I/O & Peripheral Pin TMS (General)
25VPUMPI/OMultiplexed I/O & Peripheral Pin VPUMP (General)
26TDOI/OMultiplexed I/O & Peripheral Pin TDO (General)
27TRSTI/OMultiplexed I/O & Peripheral Pin TRST (General)
28VJTAGI/OMultiplexed I/O & Peripheral Pin VJTAG (General)
29IO11RSB0I/OMultiplexed I/O & Peripheral Pin IO11RSB0 (General)
30IO10RSB0I/OMultiplexed I/O & Peripheral Pin IO10RSB0 (General)
31IO09RSB0I/OMultiplexed I/O & Peripheral Pin IO09RSB0 (General)
32IO08RSB0I/OMultiplexed I/O & Peripheral Pin IO08RSB0 (General)
33VCCIB0PowerPower Supply Input (VCCIB0 — 3.3V / 5.0V Standard Logic)
34GNDGNDGround Reference Pin (GND)
35VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
36IO07RSB0I/OMultiplexed I/O & Peripheral Pin IO07RSB0 (General)
37IO06RSB0I/OMultiplexed I/O & Peripheral Pin IO06RSB0 (General)
38GDA0/IO05RSB0I/OMultiplexed I/O & Peripheral Pin GDA0/IO05RSB0 (General)
39IO03RSB0I/OMultiplexed I/O & Peripheral Pin IO03RSB0 (General)
40GDC0/IO01RSB0I/OMultiplexed I/O & Peripheral Pin GDC0/IO01RSB0 (General)
41IO12RSB1I/OMultiplexed I/O & Peripheral Pin IO12RSB1 (General)
42IO13RSB1I/OMultiplexed I/O & Peripheral Pin IO13RSB1 (General)
43IO15RSB1I/OMultiplexed I/O & Peripheral Pin IO15RSB1 (General)
44IO16RSB1I/OMultiplexed I/O & Peripheral Pin IO16RSB1 (General)
45IO18RSB1I/OMultiplexed I/O & Peripheral Pin IO18RSB1 (General)
46IO19RSB1I/OMultiplexed I/O & Peripheral Pin IO19RSB1 (General)
47IO20RSB1I/OMultiplexed I/O & Peripheral Pin IO20RSB1 (General)
48IO21RSB1I/OMultiplexed I/O & Peripheral Pin IO21RSB1 (General)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 GEC0/IO37RSB1
I/O
Multiplexed I/O & Peripheral Pin GEC0/IO37RSB1 (General)
Design note: Signal terminal GEC0/IO37RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GEC0/IO37RSB1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: A3PN010-2QNG48 (MICROCHIP · QFN-48-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-48-EP(6x6) · 6.00×6.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
A3PN010-2QNG48 (QFN-48-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for A3PN010
P27 · p27_fig011583×612px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Figure 2-5 • Entering and Exiting Sleep Mode-Typical Timing Diagram
Figure 2-5 • Entering and Exiting Sleep Mode-Typical Timing Diagram
P27 · p27_fig021583×754px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Figure 2-6 • Controlling Power On/Off State Using Microprocessor and Power FET
Figure 2-6 • Controlling Power On/Off State Using Microprocessor and Power FET
P28 · p28_fig011583×780px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Figure 2-7 • Controlling Power On/Off State Using Microprocessor and Voltage Regulator
Figure 2-7 • Controlling Power On/Off State Using Microprocessor and Voltage Regulator
P166 · p166_fig011583×615px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Figure 7-4 • Single-Ended I/O Standard Topology
Figure 7-4 • Single-Ended I/O Standard Topology
P181 · p181_fig011583×1317px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Figure 7-12 • I/O Bank Architecture of AGLN250/A3PN250 Devices
Figure 7-12 • I/O Bank Architecture of AGLN250/A3PN250 Devices
P271 · p271_fig011700×1016px
A3PN010-2QNG48 (QFN-48-EP(6x6)) — VCC VCCI VJTAG | GND | TCK TDO | TMS VPUMP | TDI | C1 C2 | TRST | 1 TCK 2 GND 3 TDO 4 NC* 5 TMS 6 VJTAG 7 VPUMP 8 TRST 9 TDI 10 GND | Low Power Flash Device | VCC from the target board | VJTAG from the target board VCCI from the target boar
VCC VCCI VJTAG | GND | TCK TDO | TMS VPUMP | TDI | C1 C2 | TRST | 1 TCK 2 GND 3 TDO 4 NC* 5 TMS 6 VJTAG 7 VPUMP 8 TRST 9 TDI 10 GND | Low Power Flash Device | VCC from the target board | VJTAG from the target board VCCI from the target boar
P271 · p271_fig01P271
A3PN010-2QNG48 (QFN-48-EP(6x6)) — Datasheet Page 271 (p271_fig01)
Datasheet Page 271 (p271_fig01)

Technical Specifications & Part Details (A3PN010-2QNG48)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:A3PN010-2QNG48 (QFN-48-EP(6x6)) is a 48-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48-EP(6x6))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 4.60×4.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — A3PN010-2QNG48 (QFN-48-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of A3PN010-2QNG48 (QFN-48-EP(6x6))?

Manufactured by MICROCHIP, the A3PN010-2QNG48 is housed in a QFN-48-EP(6x6) package with 49 pins and a 0.40 mm lead pitch. Key pins include: 1 (GEC0/IO37RSB1: Multiplexed I/O & Peripheral Pin GEC0/IO37RSB1 (General)), 2 (IO36RSB1: Multiplexed I/O & Peripheral Pin IO36RSB1 (General)), 3 (GEA0/IO34RSB1: Multiplexed I/O & Peripheral Pin GEA0/IO34RSB1 (General)), 4 (IO22RSB1: Multiplexed I/O & Peripheral Pin IO22RSB1 (General)), 5 (GND: Ground Reference Pin (GND)), 6 (VCCIB1: Power Supply Input (VCCIB1 — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for A3PN010-2QNG48?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), A3PN010-2QNG48 (QFN-48-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.40 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 4.60 × 4.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for A3PN010-2QNG48?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for A3PN010-2QNG48 (MICROCHIP, QFN-48-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & A3PN010 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GEC0/IO37RSB1Digital_IOSignal terminal GEC0/IO37RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GEC0/IO37RSB1. Supported peripheral buses: General.
2IO36RSB1Digital_IOSignal terminal IO36RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO36RSB1. Supported peripheral buses: General.
3GEA0/IO34RSB1Digital_IOSignal terminal GEA0/IO34RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GEA0/IO34RSB1. Supported peripheral buses: General.
4IO22RSB1Digital_IOSignal terminal IO22RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO22RSB1. Supported peripheral buses: General.
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6VCCIB1Power_InPrimary positive power supply input (VCCIB1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7IO24RSB1Digital_IOSignal terminal IO24RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO24RSB1. Supported peripheral buses: General.
8IO33RSB1Digital_IOSignal terminal IO33RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO33RSB1. Supported peripheral buses: General.
9IO26RSB1Digital_IOSignal terminal IO26RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO26RSB1. Supported peripheral buses: General.
10IO32RSB1Digital_IOSignal terminal IO32RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO32RSB1. Supported peripheral buses: General.
11IO27RSB1Digital_IOSignal terminal IO27RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO27RSB1. Supported peripheral buses: General.
12IO29RSB1Digital_IOSignal terminal IO29RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO29RSB1. Supported peripheral buses: General.
13IO30RSB1Digital_IOSignal terminal IO30RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO30RSB1. Supported peripheral buses: General.
14IO31RSB1Digital_IOSignal terminal IO31RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO31RSB1. Supported peripheral buses: General.
15IO28RSB1Digital_IOSignal terminal IO28RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO28RSB1. Supported peripheral buses: General.
16IO25RSB1Digital_IOSignal terminal IO25RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO25RSB1. Supported peripheral buses: General.
17IO23RSB1Digital_IOSignal terminal IO23RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO23RSB1. Supported peripheral buses: General.
18VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19VCCIB1Power_InPrimary positive power supply input (VCCIB1) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
20Revision4 (August2012)Digital_IOSignal terminal Revision4 (August2012) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Revision4 (August2012). Supported peripheral buses: General.
21IO14RSB1Digital_IOSignal terminal IO14RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO14RSB1. Supported peripheral buses: General.
22TCKDigital_IOSignal terminal TCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCK. Supported peripheral buses: General.
23TDIDigital_IOSignal terminal TDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDI. Supported peripheral buses: General.
24TMSDigital_IOSignal terminal TMS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS. Supported peripheral buses: General.
25VPUMPDigital_IOSignal terminal VPUMP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VPUMP. Supported peripheral buses: General.
26TDODigital_IOSignal terminal TDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDO. Supported peripheral buses: General.
27TRSTDigital_IOSignal terminal TRST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TRST. Supported peripheral buses: General.
28VJTAGDigital_IOSignal terminal VJTAG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VJTAG. Supported peripheral buses: General.
29IO11RSB0Digital_IOSignal terminal IO11RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO11RSB0. Supported peripheral buses: General.
30IO10RSB0Digital_IOSignal terminal IO10RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO10RSB0. Supported peripheral buses: General.
31IO09RSB0Digital_IOSignal terminal IO09RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO09RSB0. Supported peripheral buses: General.
32IO08RSB0Digital_IOSignal terminal IO08RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO08RSB0. Supported peripheral buses: General.
33VCCIB0Power_InPrimary positive power supply input (VCCIB0) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36IO07RSB0Digital_IOSignal terminal IO07RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO07RSB0. Supported peripheral buses: General.
37IO06RSB0Digital_IOSignal terminal IO06RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO06RSB0. Supported peripheral buses: General.
38GDA0/IO05RSB0Digital_IOSignal terminal GDA0/IO05RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GDA0/IO05RSB0. Supported peripheral buses: General.
39IO03RSB0Digital_IOSignal terminal IO03RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO03RSB0. Supported peripheral buses: General.
40GDC0/IO01RSB0Digital_IOSignal terminal GDC0/IO01RSB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GDC0/IO01RSB0. Supported peripheral buses: General.
41IO12RSB1Digital_IOSignal terminal IO12RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO12RSB1. Supported peripheral buses: General.
42IO13RSB1Digital_IOSignal terminal IO13RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO13RSB1. Supported peripheral buses: General.
43IO15RSB1Digital_IOSignal terminal IO15RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO15RSB1. Supported peripheral buses: General.
44IO16RSB1Digital_IOSignal terminal IO16RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO16RSB1. Supported peripheral buses: General.
45IO18RSB1Digital_IOSignal terminal IO18RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO18RSB1. Supported peripheral buses: General.
46IO19RSB1Digital_IOSignal terminal IO19RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO19RSB1. Supported peripheral buses: General.
47IO20RSB1Digital_IOSignal terminal IO20RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO20RSB1. Supported peripheral buses: General.
48IO21RSB1Digital_IOSignal terminal IO21RSB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IO21RSB1. Supported peripheral buses: General.
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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