![A40MX02-FPQG100 (PQFP-100(14x20)) — Figure 43 • PQ160 [PQFP-160(28x28)]](/api/v1/assets/C2615737/extracted/pinout_diagram.png)
![A40MX02-FPQG100 (PQFP-100(14x20)) — Figure 48 • TQ176 [LQFP-176(24x24)]](/api/v1/assets/C2616396/extracted/pinout_diagram.png)
![A40MX02-FPQG100 (PQFP-100(14x20)) — Figure 51 • BG272 [PBGA-272]](/api/v1/assets/C2616241/extracted/pinout_diagram.png)
PQFP-100(14x20) · 100P
100P20.0×14.0×1.60mmP=0.65mm
A40MX02 / A40MX04 / A42MX09 (PQFP-100(14x20))
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 2 | DCLK I/O , | I/O | Multiplexed I/O & Peripheral Pin DCLK I/O , (General) |
| 3 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 4 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 5 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 6 | WD I/O , | I/O | Multiplexed I/O & Peripheral Pin WD I/O , (General) |
| 7 | WD I/O , | I/O | Multiplexed I/O & Peripheral Pin WD I/O , (General) |
| 8 | VCCI | Power | Power Supply Input (VCCI — 3.3V / 5.0V Standard Logic) |
| 9 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 10 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 11 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 12 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 13 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 14 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 15 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 16 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 17 | VCCA | Power | Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic) |
| 18 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 19 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 20 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 21 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 22 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 23 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 24 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 25 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 26 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 27 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 28 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 29 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 30 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 31 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 32 | GND | GND | Ground Reference Pin (GND) |
| 33 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 34 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 35 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 36 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 37 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 38 | VCCA | Power | Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic) |
| 39 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 40 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 41 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 42 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 43 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 44 | GND | GND | Ground Reference Pin (GND) |
| 45 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 46 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 47 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 48 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 49 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 50 | SDO I/O , | I/O | Multiplexed I/O & Peripheral Pin SDO I/O , (General) |
| 51 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 52 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 53 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 54 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 55 | GND | GND | Ground Reference Pin (GND) |
| 56 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 57 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 58 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 59 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 60 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 61 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 62 | LP | I/O | Multiplexed I/O & Peripheral Pin LP (General) |
| 63 | VCCA | Power | Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic) |
| 64 | VCCI | Power | Power Supply Input (VCCI — 3.3V / 5.0V Standard Logic) |
| 65 | VCCA | Power | Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic) |
| 66 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 67 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 68 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 69 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 70 | GND | GND | Ground Reference Pin (GND) |
| 71 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 72 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 73 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 74 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 75 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 76 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 77 | SDI I/O , | I/O | Multiplexed I/O & Peripheral Pin SDI I/O , (General) |
| 78 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 79 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 80 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 81 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 82 | GND | GND | Ground Reference Pin (GND) |
| 83 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 84 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 85 | PRA I/O , | I/O | Multiplexed I/O & Peripheral Pin PRA I/O , (General) |
| 86 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 87 | CLKA I/O , | I/O | Multiplexed I/O & Peripheral Pin CLKA I/O , (General) |
| 88 | VCCA | Power | Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic) |
| 89 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 90 | CLKB I/O , | I/O | Multiplexed I/O & Peripheral Pin CLKB I/O , (General) |
| 91 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 92 | PRB I/O , | I/O | Multiplexed I/O & Peripheral Pin PRB I/O , (General) |
| 93 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 94 | GND | GND | Ground Reference Pin (GND) |
| 95 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 96 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 97 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 98 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 99 | I/O | I/O | Multiplexed I/O & Peripheral Pin I/O (General) |
| 100 | DCLK I/O , | I/O | Multiplexed I/O & Peripheral Pin DCLK I/O , (General) |
PIN 1 I/O
I/OMultiplexed I/O & Peripheral Pin I/O (General)
Design note: I/O
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PQFP-100(14x20) · 14.00×20.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for A40MX02 / A40MX04 / A42MX09
P103 · p103_fig01EXACT PACKAGE
P133 · p133_fig01EXACT PACKAGE
P1 · p01_fig01654×162px
P96 · p96_fig01843×871px
P133 · p133_fig01P133
P112 · p112_fig01EXACT PACKAGE
P136 · p136_fig01EXACT PACKAGE
P155 · p155_fig01EXACT PACKAGE
Technical Specifications & Part Details (A40MX02-FPQG100)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:A40MX02-FPQG100 (PQFP-100(14x20)) is a 100-pin standard electronic & interconnect component featuring a 20.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
20.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: TQFP (PQFP-100(14x20))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — A40MX02 / A40MX04 / A42MX09 (11)
PQFP-100(14x20) · 100P
100P20.0×14.0×1.60mmP=0.65mm
A40MX02 / A40MX04 / A42MX09 (PQFP-100(14x20))
PQFP-160(28x28) · 160P
160P28.0×28.0×1.60mmP=0.65mm
A40MX02 / A40MX04 / A42MX09 (PQFP-160(28x28))
LQFP-176(24x24) · 176P
176P24.0×24.0×1.40mmP=0.5mm
A40MX02 / A40MX04 / A42MX09 (LQFP-176(24x24))
PBGA-272 · 272P
IPC-7351B
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
IPC-7351B
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
IPC-7351B
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
IPC-7351B
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
PBGA-272 · 272P
IPC-7351B
272P27.0×27.0×1.35mmP=1.27mm
A40MX02 / A40MX04 / A42MX09 (PBGA-272)
Mechanical Dimensions & Land Pattern (PQFP-100(14x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.65mm
Pad Size (W × L)Level B
0.36 × 2.41 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit PQFP-100(14x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — A40MX02-FPQG100 (PQFP-100(14x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of A40MX02-FPQG100 (PQFP-100(14x20))?
Manufactured by MICROCHIP, the A40MX02-FPQG100 is housed in a PQFP-100(14x20) package with 100 pins and a 0.65 mm lead pitch. Key pins include: 1 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 2 (DCLK I/O ,: Multiplexed I/O & Peripheral Pin DCLK I/O , (General)), 3 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 4 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 5 (I/O: Multiplexed I/O & Peripheral Pin I/O (General)), 6 (WD I/O ,: Multiplexed I/O & Peripheral Pin WD I/O , (General)).
What are the IPC-7351B PCB Footprint dimensions for A40MX02-FPQG100?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), A40MX02-FPQG100 (PQFP-100(14x20)) has a nominal body envelope of 14.00 × 20.00 mm, pitch e = 0.65 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for A40MX02-FPQG100?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for A40MX02-FPQG100 (MICROCHIP, PQFP-100(14x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & A40MX02 / A40MX04 / A42MX09 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 2 | DCLK I/O , | Digital_IO | Signal terminal DCLK I/O , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCLK I/O ,. Supported peripheral buses: General. |
| 3 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 4 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 5 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 6 | WD I/O , | Digital_IO | Signal terminal WD I/O , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WD I/O ,. Supported peripheral buses: General. |
| 7 | WD I/O , | Digital_IO | Signal terminal WD I/O , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WD I/O ,. Supported peripheral buses: General. |
| 8 | VCCI | Power_In | Primary positive power supply input (VCCI) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 10 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 11 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 12 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 13 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 14 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 15 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 16 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 17 | VCCA | Power_In | Primary positive power supply input (VCCA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 18 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 19 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 20 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 21 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 22 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 23 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 24 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 25 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 26 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 27 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 28 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 29 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 30 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 31 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 32 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 33 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 34 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 35 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 36 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 37 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 38 | VCCA | Power_In | Primary positive power supply input (VCCA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 39 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 40 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 41 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 42 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 43 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 44 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 45 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 46 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 47 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 48 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 49 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 50 | SDO I/O , | Digital_IO | Signal terminal SDO I/O , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDO I/O ,. Supported peripheral buses: General. |
| 51 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 52 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 53 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 54 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 55 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 56 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 57 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 58 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 59 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 60 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 61 | I/O | Digital_IO | Signal terminal I/O (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O. Supported peripheral buses: General. |
| 62 | LP | Digital_IO | Signal terminal LP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LP. Supported peripheral buses: General. |
| 63 | VCCA | Power_In | Primary positive power supply input (VCCA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 64 | VCCI | Power_In | Primary positive power supply input (VCCI) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |