Mechanical Dimensions & Land Pattern (CSPBGA-324)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
11.00 × 11.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.50mm
Pad Size (W × L)Level B
0.24 × 0.24 mm
Pins / Total PadsTopology
325P / 325Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit CSPBGA-324 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — M2GL090TS-1FCSG325I (CSPBGA-324)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of M2GL090TS-1FCSG325I (CSPBGA-324)?
Manufactured by MICROCHIP, the M2GL090TS-1FCSG325I is housed in a CSPBGA-324 package with 325 pins and a 0.50 mm lead pitch. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (DDRIO39NB0/MDDR_ADDR7: Multiplexed I/O & Peripheral Pin DDRIO39NB0/MDDR_ADDR7 (General)), A3 (DDRIO39PB0/MDDR_ODT: Multiplexed I/O & Peripheral Pin DDRIO39PB0/MDDR_ODT (General)), A4 (DDRIO43NB0/MDDR_ADDR0: Multiplexed I/O & Peripheral Pin DDRIO43NB0/MDDR_ADDR0 (General)), A5 (DDRIO41PB0/MDDR_ADDR3: Multiplexed I/O & Peripheral Pin DDRIO41PB0/MDDR_ADDR3 (General)), A6 (VSS: Ground Reference Pin (VSS)).
What are the IPC-7351B PCB Footprint dimensions for M2GL090TS-1FCSG325I?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), M2GL090TS-1FCSG325I (CSPBGA-324) has a nominal body envelope of 11.00 × 11.00 mm, pitch e = 0.50 mm, and 325 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for M2GL090TS-1FCSG325I?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for M2GL090TS-1FCSG325I (MICROCHIP, CSPBGA-324) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (325 pins) & M2GL010TS / M2GL025 / M2GL025TS Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A2 | DDRIO39NB0/MDDR_ADDR7 | Digital_IO | Signal terminal DDRIO39NB0/MDDR_ADDR7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO39NB0/MDDR_ADDR7. Supported peripheral buses: General. |
| A3 | DDRIO39PB0/MDDR_ODT | Digital_IO | Signal terminal DDRIO39PB0/MDDR_ODT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO39PB0/MDDR_ODT. Supported peripheral buses: General. |
| A4 | DDRIO43NB0/MDDR_ADDR0 | Digital_IO | Signal terminal DDRIO43NB0/MDDR_ADDR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO43NB0/MDDR_ADDR0. Supported peripheral buses: General. |
| A5 | DDRIO41PB0/MDDR_ADDR3 | Digital_IO | Signal terminal DDRIO41PB0/MDDR_ADDR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO41PB0/MDDR_ADDR3. Supported peripheral buses: General. |
| A6 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A7 | DDRIO45NB0/MDDR_CLK_N | Digital_IO | Signal terminal DDRIO45NB0/MDDR_CLK_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO45NB0/MDDR_CLK_N. Supported peripheral buses: General. |
| A8 | DDRIO48PB0/MDDR_RAS_N | Digital_IO | Signal terminal DDRIO48PB0/MDDR_RAS_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO48PB0/MDDR_RAS_N. Supported peripheral buses: General. |
| A9 | DDRIO48NB0/MDDR_WE_N | Digital_IO | Signal terminal DDRIO48NB0/MDDR_WE_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO48NB0/MDDR_WE_N. Supported peripheral buses: General. |
| A10 | DDRIO49NB0/MDDR_DQ15 | Digital_IO | Signal terminal DDRIO49NB0/MDDR_DQ15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO49NB0/MDDR_DQ15. Supported peripheral buses: General. |
| A11 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A12 | IOA12 | Digital_IO | General Purpose Digital I/O Pin IOA12 |
| A13 | DDRIO57NB0/MDDR_DQ4 | Digital_IO | Signal terminal DDRIO57NB0/MDDR_DQ4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO57NB0/MDDR_DQ4. Supported peripheral buses: General. |
| A14 | DDRIO56PB0/MDDR_DQ5 | Digital_IO | Signal terminal DDRIO56PB0/MDDR_DQ5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO56PB0/MDDR_DQ5. Supported peripheral buses: General. |
| A15 | DDRIO58PB0/MDDR_DQS0 | Digital_IO | Signal terminal DDRIO58PB0/MDDR_DQS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO58PB0/MDDR_DQS0. Supported peripheral buses: General. |
| A16 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A17 | DDRIO61NB0 | Digital_IO | Signal terminal DDRIO61NB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO61NB0. Supported peripheral buses: General. |
| A18 | IOA18 | Digital_IO | General Purpose Digital I/O Pin IOA18 |
| A19 | IOA19 | Digital_IO | General Purpose Digital I/O Pin IOA19 |
| A20 | IOA20 | Digital_IO | General Purpose Digital I/O Pin IOA20 |
| A21 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| B1 | DDRIO37NB0/MDDR_ADDR11 | Digital_IO | Signal terminal DDRIO37NB0/MDDR_ADDR11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO37NB0/MDDR_ADDR11. Supported peripheral buses: General. |
| B2 | DDRIO37PB0/MDDR_ADDR10 | Digital_IO | Signal terminal DDRIO37PB0/MDDR_ADDR10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO37PB0/MDDR_ADDR10. Supported peripheral buses: General. |
| B3 | VDDI0 | Power_In | Primary positive power supply input (VDDI0) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| B4 | DDRIO43PB0/MDDR_BA2 | Digital_IO | Signal terminal DDRIO43PB0/MDDR_BA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO43PB0/MDDR_BA2. Supported peripheral buses: General. |
| B5 | DDRIO41NB0/MDDR_ADDR4 | Digital_IO | Signal terminal DDRIO41NB0/MDDR_ADDR4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO41NB0/MDDR_ADDR4. Supported peripheral buses: General. |
| B6 | DDRIO44NB0/MDDR_BA1 | Digital_IO | Signal terminal DDRIO44NB0/MDDR_BA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO44NB0/MDDR_BA1. Supported peripheral buses: General. |
| B7 | DDRIO45PB0/MDDR_CLK | Digital_IO | Signal terminal DDRIO45PB0/MDDR_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO45PB0/MDDR_CLK. Supported peripheral buses: General. |
| B8 | VDDI0 | Power_In | Primary positive power supply input (VDDI0) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| B9 | IOB9 | Digital_IO | General Purpose Digital I/O Pin IOB9 |
| B10 | DDRIO52NB0/MDDR_DQS1_N | Digital_IO | Signal terminal DDRIO52NB0/MDDR_DQS1_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO52NB0/MDDR_DQS1_N. Supported peripheral buses: General. |
| B11 | DDRIO54NB0/MDDR_DQ9 | Digital_IO | Signal terminal DDRIO54NB0/MDDR_DQ9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO54NB0/MDDR_DQ9. Supported peripheral buses: General. |
| B12 | DDRIO54PB0/MDDR_DQ8 | Digital_IO | Signal terminal DDRIO54PB0/MDDR_DQ8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO54PB0/MDDR_DQ8. Supported peripheral buses: General. |
| B13 | VDDI0 | Power_In | Primary positive power supply input (VDDI0) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| B14 | DDRIO56NB0/MDDR_DQ6 | Digital_IO | Signal terminal DDRIO56NB0/MDDR_DQ6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO56NB0/MDDR_DQ6. Supported peripheral buses: General. |
| B15 | DDRIO58NB0/MDDR_DQS0_N | Digital_IO | Signal terminal DDRIO58NB0/MDDR_DQS0_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO58NB0/MDDR_DQS0_N. Supported peripheral buses: General. |
| B16 | IOB16 | Digital_IO | General Purpose Digital I/O Pin IOB16 |
| B17 | IOB17 | Digital_IO | General Purpose Digital I/O Pin IOB17 |
| B18 | VDDI0 | Power_In | Primary positive power supply input (VDDI0) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| B19 | IOB19 | Digital_IO | General Purpose Digital I/O Pin IOB19 |
| B20 | IOB20 | Digital_IO | General Purpose Digital I/O Pin IOB20 |
| B21 | MSIO82NB7 | Digital_IO | Signal terminal MSIO82NB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MSIO82NB7. Supported peripheral buses: General. |
| C1 | DDRIO35PB0/MDDR_ADDR14 | Digital_IO | Signal terminal DDRIO35PB0/MDDR_ADDR14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO35PB0/MDDR_ADDR14. Supported peripheral buses: General. |
| C2 | DDRIO35NB0/MDDR_ADDR15 | Digital_IO | Signal terminal DDRIO35NB0/MDDR_ADDR15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO35NB0/MDDR_ADDR15. Supported peripheral buses: General. |
| C6 | DDRIO44PB0/MDDR_BA0 | Digital_IO | Signal terminal DDRIO44PB0/MDDR_BA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO44PB0/MDDR_BA0. Supported peripheral buses: General. |
| C11 | IOC11 | Digital_IO | General Purpose Digital I/O Pin IOC11 |
| C16 | IOC16 | Digital_IO | General Purpose Digital I/O Pin IOC16 |
| C20 | MSIO85PB7 | Digital_IO | Signal terminal MSIO85PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MSIO85PB7. Supported peripheral buses: General. |
| C21 | MSIO82PB7 | Digital_IO | Signal terminal MSIO82PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MSIO82PB7. Supported peripheral buses: General. |
| D1 | IOD1 | Digital_IO | General Purpose Digital I/O Pin IOD1 |
| D2 | MSIO28NB1 | Digital_IO | Signal terminal MSIO28NB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MSIO28NB1. Supported peripheral buses: General. |
| D4 | DDRIO36NB0/MDDR_ADDR13 | Digital_IO | Signal terminal DDRIO36NB0/MDDR_ADDR13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO36NB0/MDDR_ADDR13. Supported peripheral buses: General. |
| D5 | DDRIO40PB0/MDDR_ADDR5 | Digital_IO | Signal terminal DDRIO40PB0/MDDR_ADDR5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO40PB0/MDDR_ADDR5. Supported peripheral buses: General. |
| D6 | DDRIO40NB0/MDDR_ADDR6 | Digital_IO | Signal terminal DDRIO40NB0/MDDR_ADDR6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO40NB0/MDDR_ADDR6. Supported peripheral buses: General. |
| D7 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| D8 | DDRIO46NB0/MDDR_CAS_N | Digital_IO | Signal terminal DDRIO46NB0/MDDR_CAS_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO46NB0/MDDR_CAS_N. Supported peripheral buses: General. |
| D9 | IOD9 | Digital_IO | General Purpose Digital I/O Pin IOD9 |
| D10 | IOD10 | Digital_IO | General Purpose Digital I/O Pin IOD10 |
| D11 | IOD11 | Digital_IO | General Purpose Digital I/O Pin IOD11 |
| D12 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| D13 | DDRIO60PB0/MDDR_DQ0 | Digital_IO | Signal terminal DDRIO60PB0/MDDR_DQ0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO60PB0/MDDR_DQ0. Supported peripheral buses: General. |
| D14 | DDRIO59PB0/MDDR_DQ2 | Digital_IO | Signal terminal DDRIO59PB0/MDDR_DQ2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO59PB0/MDDR_DQ2. Supported peripheral buses: General. |
| D15 | DDRIO59NB0/MDDR_DQ3 | Digital_IO | Signal terminal DDRIO59NB0/MDDR_DQ3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDRIO59NB0/MDDR_DQ3. Supported peripheral buses: General. |
| D16 | IOD16 | Digital_IO | General Purpose Digital I/O Pin IOD16 |