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STM32H7S3V8H6 (TFBGA-100(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H7S3V8H6

STTFBGA-100(8x8) · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H7S3V8H6 (TFBGA-100(8x8))A1PB8A2PB6A3PB3A4BOOT0A5PM14A6PM12A7PM9A8PM6A9PM8A10PM2B1IOB1B2PB9B3PB7B4PB4B5PM13B6PM11B7DVDDB8PM5B9PM3B10PM1C1VSSC2IOC2C3VBATC4VCAP4C5VSSC6VDD50USBC7VSSC8PM0C9PA14C10PA15D1VDDSMPSD2VSSSMPSD3PC13D4PB5D5VDDD6VSSUSBD7VDD33USBD8VCAP3D9PA12D10PA13E1VFBSMPSE2VLXSMPSE3VDDE4VSSE5VDDLDOE6VDDLDOE7VDDE8PA8E9PA10E10PA11K10PP1K9PO2K8PP0K7PO4K6PP3K5PP4K4PB1K3PA6K2PA4K1PA0J10PB11J9PP7J8PP6J7PP5J6PO5J5PP2J4PO1J3PA7J2PA2J1VREFPH10PB13H9PB10H8PO0H7VDDXSPI1H6VSSH5VDDXSPI1H4VSSH3PA5H2VDDAH1PC1G10PB15G9PB12G8VCAP2G7VDDG6VDDXSPI1G5PB2G4VDDG3VSSAG2PA1G1PC0F10PA9F9PB14F8VSSF7VDDLDOF6VSSF5PB0F4VREFMF3NRSTF2PH1 - OSC OUF1PH0 - OSC INGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A2PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
A3PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PM14I/OMultiplexed I/O & Peripheral Pin PM14 (General)
A6PM12I/OMultiplexed I/O & Peripheral Pin PM12 (General)
A7PM9I/OMultiplexed I/O & Peripheral Pin PM9 (General)
A8PM6I/OMultiplexed I/O & Peripheral Pin PM6 (General)
A9PM8I/OMultiplexed I/O & Peripheral Pin PM8 (General)
A10PM2I/OMultiplexed I/O & Peripheral Pin PM2 (General)
B1IOB1I/OGeneral Purpose Digital I/O Pin IOB1
B2PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C)
B3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B5PM13I/OMultiplexed I/O & Peripheral Pin PM13 (General)
B6PM11I/OMultiplexed I/O & Peripheral Pin PM11 (General)
B7DVDDPowerPower Supply Input (DVDD — 3.3V VDD (Max 4.0V))
B8PM5I/OMultiplexed I/O & Peripheral Pin PM5 (General)
B9PM3I/OMultiplexed I/O & Peripheral Pin PM3 (General)
B10PM1I/OMultiplexed I/O & Peripheral Pin PM1 (General)
C1VSSGNDGround Reference Pin (VSS)
C2IOC2I/OGeneral Purpose Digital I/O Pin IOC2
C3VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C4VCAP4I/OMultiplexed I/O & Peripheral Pin VCAP4 (General)
C5VSSGNDGround Reference Pin (VSS)
C6VDD50USBPowerPower Supply Input (VDD50USB — 3.3V VDD (Max 4.0V))
C7VSSGNDGround Reference Pin (VSS)
C8PM0I/OMultiplexed I/O & Peripheral Pin PM0 (General)
C9PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
C10PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
D1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
D2VSSSMPSGNDGround Reference Pin (VSSSMPS)
D3PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
D4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
D5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D6VSSUSBGNDGround Reference Pin (VSSUSB)
D7VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
D8VCAP3I/OMultiplexed I/O & Peripheral Pin VCAP3 (General)
D9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
D10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
E1VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
E2VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
E3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E4VSSGNDGround Reference Pin (VSS)
E5VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
E6VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
E7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E8PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E9PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
E10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
F1PH0 - OSC IN(PH_ 0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC IN(PH_ 0) (RTC/CLK)
F2PH1 - OSC OUT(_ PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(_ PH1) (RTC/CLK)
F3NRSTISystem Enable & Hardware Reset (NRST)
F4VREFMAnalogMultiplexed I/O & Peripheral Pin VREFM (General)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
F6VSSGNDGround Reference Pin (VSS)
F7VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
F8VSSGNDGround Reference Pin (VSS)
F9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
F10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
G1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
G2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
G3VSSAGNDGround Reference Pin (VSSA)
G4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK)
G6VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
G7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G8VCAP2I/OMultiplexed I/O & Peripheral Pin VCAP2 (General)
G9PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
G10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
H1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
H2VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
H4VSSGNDGround Reference Pin (VSS)
H5VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
H6VSSGNDGround Reference Pin (VSS)
H7VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
H8PO0I/OMultiplexed I/O & Peripheral Pin PO0 (General)
H9PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
H10PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
J1VREFPAnalogMultiplexed I/O & Peripheral Pin VREFP (General)
J2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
J3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
J4PO1I/OMultiplexed I/O & Peripheral Pin PO1 (General)
J5PP2I/OMultiplexed I/O & Peripheral Pin PP2 (General)
J6PO5I/OMultiplexed I/O & Peripheral Pin PO5 (General)
J7PP5I/OMultiplexed I/O & Peripheral Pin PP5 (General)
J8PP6I/OMultiplexed I/O & Peripheral Pin PP6 (General)
J9PP7I/OMultiplexed I/O & Peripheral Pin PP7 (General)
J10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
K1PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
K2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
K3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
K4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
K5PP4I/OMultiplexed I/O & Peripheral Pin PP4 (General)
K6PP3I/OMultiplexed I/O & Peripheral Pin PP3 (General)
K7PO4I/OMultiplexed I/O & Peripheral Pin PO4 (General)
K8PP0I/OMultiplexed I/O & Peripheral Pin PP0 (General)
K9PO2I/OMultiplexed I/O & Peripheral Pin PO2 (General)
K10PP1I/OMultiplexed I/O & Peripheral Pin PP1 (General)
PIN A1 PB8
I/O
Multiplexed I/O & Peripheral Pin PB8 (General)
Design note: Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H7S3V8H6 (ST · TFBGA-100(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H7S3V8H6 (TFBGA-100(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H7S3V8H6 (TFBGA-100(8x8)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H7S3V8H6 (TFBGA-100(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H7S3V8H6 (TFBGA-100(8x8)) - 4. Package Dimensions (D×E×A)
TFBGA-100(8x8) · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H7S3V8H6 (TFBGA-100(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H7S3V8H6 (TFBGA-100(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for STM32H7S3L8H / STM32H7S3V8H
P76 · p76_fig01EXACT PACKAGE
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 6. TFBGA100 SMPS pinout(a)
Figure 6. TFBGA100 SMPS pinout(a)
P293 · p293_fig01EXACT PACKAGE
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 84. TFBGA100 - Recommended footprint
Figure 84. TFBGA100 - Recommended footprint
P1 · p01_fig01881×841px
STM32H7S3V8H6 (TFBGA-100(8x8)) — • 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
• 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
P77 · p77_fig011547×1521px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 7. UFBGA144 SMPS pinout(a)
Figure 7. UFBGA144 SMPS pinout(a)
P78 · p78_fig011587×1450px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 8. UFBGA169 SMPS pinout(a)
Figure 8. UFBGA169 SMPS pinout(a)
P150 · p150_fig011619×2259px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 23. Power supply scheme
Figure 23. Power supply scheme
P193 · p193_fig011546×500px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 35. Typical application with an 8 MHz crystal
Figure 35. Typical application with an 8 MHz crystal
P194 · p194_fig011546×516px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 36. Typical application with a 32.768 kHz crystal
Figure 36. Typical application with a 32.768 kHz crystal
P299 · p299_fig011546×1295px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 88. UFBGA144 - Recommended footprint
Figure 88. UFBGA144 - Recommended footprint
P311 · p311_fig011546×1305px
STM32H7S3V8H6 (TFBGA-100(8x8)) — Figure 97. UFBGA(176+25) - Recommended footprint
Figure 97. UFBGA(176+25) - Recommended footprint

Technical Specifications & Part Details (STM32H7S3V8H6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H7S3V8H6 (TFBGA-100(8x8)) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
600 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
15 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100(8x8))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H7S3V8H6 (TFBGA-100(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H7S3V8H6 (TFBGA-100(8x8))?

Manufactured by ST, the STM32H7S3V8H6 is housed in a TFBGA-100(8x8) package with 100 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A2 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A3 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PM14: Multiplexed I/O & Peripheral Pin PM14 (General)), A6 (PM12: Multiplexed I/O & Peripheral Pin PM12 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H7S3V8H6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7S3V8H6 (TFBGA-100(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7S3V8H6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7S3V8H6 (ST, TFBGA-100(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H7S3L8H / STM32H7S3V8H Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A2PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
A3PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PM14Digital_IOSignal terminal PM14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM14. Supported peripheral buses: General.
A6PM12Digital_IOSignal terminal PM12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM12. Supported peripheral buses: General.
A7PM9Digital_IOSignal terminal PM9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM9. Supported peripheral buses: General.
A8PM6Digital_IOSignal terminal PM6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM6. Supported peripheral buses: General.
A9PM8Digital_IOSignal terminal PM8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM8. Supported peripheral buses: General.
A10PM2Digital_IOSignal terminal PM2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM2. Supported peripheral buses: General.
B1IOB1Digital_IOGeneral Purpose Digital I/O Pin IOB1
B2PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
B3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B5PM13Digital_IOSignal terminal PM13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM13. Supported peripheral buses: General.
B6PM11Digital_IOSignal terminal PM11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM11. Supported peripheral buses: General.
B7DVDDPower_InPrimary positive power supply input (DVDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B8PM5Digital_IOSignal terminal PM5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM5. Supported peripheral buses: General.
B9PM3Digital_IOSignal terminal PM3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM3. Supported peripheral buses: General.
B10PM1Digital_IOSignal terminal PM1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM1. Supported peripheral buses: General.
C1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C2IOC2Digital_IOGeneral Purpose Digital I/O Pin IOC2
C3VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C4VCAP4Digital_IOSignal terminal VCAP4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP4. Supported peripheral buses: General.
C5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C6VDD50USBPower_InPrimary positive power supply input (VDD50USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C8PM0Digital_IOSignal terminal PM0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM0. Supported peripheral buses: General.
C9PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C10PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
D1VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
D3PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
D4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
D5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D6VSSUSBGND0V electrical ground return terminal (VSSUSB) for internal core logic, I/O drivers, and analog sub-blocks.
D7VDD33USBPower_InPrimary positive power supply input (VDD33USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D8VCAP3Digital_IOSignal terminal VCAP3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP3. Supported peripheral buses: General.
D9PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
D10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
E1VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
E2VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
E3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E5VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E8PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E9PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
E10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
F1PH0 - OSC IN(PH_ 0)Digital_IOSignal terminal PH0 - OSC IN(PH_ 0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC IN(PH_ 0). Supported peripheral buses: RTC/CLK.
F2PH1 - OSC OUT(_ PH1)Digital_IOSignal terminal PH1 - OSC OUT(_ PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT(_ PH1). Supported peripheral buses: RTC/CLK.
F3NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F4VREFMAnalogSignal terminal VREFM (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREFM. Supported peripheral buses: General.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, PWM.
F6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F7VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F9PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
F10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
G1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
G2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
G3VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
G4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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