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CH339W (QFN-68(8x8)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH339W

WCHID: C25503971QFN-68(8x8) · 69 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH339W (QFN-68(8x8))1MDITP2MDITN3VDD334MDIRP5MDIRN6GND7NC8IO09IO410DP711VDD3312IO713IO1514GND15XO16XI17AVDDK18IO1919IO2020IO921IO1022GND23VDD3324IO1325IO1426IO2127IO4728IO3329IO2930VDD3331LED_ACT/CFG032RXD/OVCUR3#33TXD/OVCUR2#34OVCUR1#35LED_LINK/CFG69EP68TDI/PWREN7#67TDO/PWREN6#66TMS/PWREN5#65TCK/PWREN4#64TRST/PWREN3#63VIO3362SRST/PWREN2#61GND60DVDDK59PD_CTL1/GPIO58RESET#57PWR_CC256PWR_CC155SD_CMD/PSELF54VSDIO53GND52SD_SCK51SD_D050SD_D149SD_D248SD_D347HUB_CC46SDVCC_EN/CFG45MISO/OVCUR7#44MOSI/OVCUR6#43SCS/OVCUR5#42SCK/OVCUR4#41PWREN1#40VIO3339SCL/SMBCLK/R38SDA/SMBDAT/C37PD_CIL2/GPIO36PD_CTL3/GPIOGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.250.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869E=8.00mm · Pitch e=0.40mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (69/69)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MDITPI/OMultiplexed I/O & Peripheral Pin MDITP (General)
2MDITNI/OMultiplexed I/O & Peripheral Pin MDITN (General)
3VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
4MDIRPI/OMultiplexed I/O & Peripheral Pin MDIRP (General)
5MDIRNI/OMultiplexed I/O & Peripheral Pin MDIRN (General)
6GNDGNDGround Reference Pin (GND)
7NCNCNo Connect (Leave Floating)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10DP7I/OMultiplexed I/O & Peripheral Pin DP7 (General)
11VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14GNDGNDGround Reference Pin (GND)
15XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
16XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
17AVDDKPowerPower Supply Input (AVDDK — 3.3V / 5.0V Standard Logic)
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22GNDGNDGround Reference Pin (GND)
23VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
24IO13I/OGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14I/OGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26IO21I/OGPIO21 / RTC_GPIO21
27IO47I/OGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33I/OGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29IO29I/OGeneral Purpose Digital I/O Pin IO29
30VDD33PowerPower Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
31LED_ACT/CFG0I/OMultiplexed I/O & Peripheral Pin LED_ACT/CFG0 (General)
32RXD/OVCUR3#I/OMultiplexed I/O & Peripheral Pin RXD/OVCUR3# (UART)
33TXD/OVCUR2#I/OMultiplexed I/O & Peripheral Pin TXD/OVCUR2# (UART)
34OVCUR1#I/OMultiplexed I/O & Peripheral Pin OVCUR1# (General)
35LED_LINK/CFG1I/OMultiplexed I/O & Peripheral Pin LED_LINK/CFG1 (General)
36PD_CTL3/GPIO3I/OMultiplexed I/O & Peripheral Pin PD_CTL3/GPIO3 (General)
37PD_CIL2/GPIO2I/OMultiplexed I/O & Peripheral Pin PD_CIL2/GPIO2 (General)
38SDA/SMBDAT/CTSI/OMultiplexed I/O & Peripheral Pin SDA/SMBDAT/CTS (UART, I2C)
39SCL/SMBCLK/RTSI/OMultiplexed I/O & Peripheral Pin SCL/SMBCLK/RTS (UART, I2C)
40VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
41PWREN1#I/OMultiplexed I/O & Peripheral Pin PWREN1# (General)
42SCK/OVCUR4#I/OMultiplexed I/O & Peripheral Pin SCK/OVCUR4# (SPI)
43SCS/OVCUR5#I/OMultiplexed I/O & Peripheral Pin SCS/OVCUR5# (General)
44MOSI/OVCUR6#I/OMultiplexed I/O & Peripheral Pin MOSI/OVCUR6# (SPI)
45MISO/OVCUR7#I/OMultiplexed I/O & Peripheral Pin MISO/OVCUR7# (SPI)
46SDVCC_EN/CFG2PowerPower Supply Input (SDVCC_EN/CFG2 — 3.3V / 5.0V Standard Logic)
47HUB_CCI/OMultiplexed I/O & Peripheral Pin HUB_CC (General)
48SD_D3I/OMultiplexed I/O & Peripheral Pin SD_D3 (General)
49SD_D2I/OMultiplexed I/O & Peripheral Pin SD_D2 (General)
50SD_D1I/OMultiplexed I/O & Peripheral Pin SD_D1 (General)
51SD_D0I/OMultiplexed I/O & Peripheral Pin SD_D0 (General)
52SD_SCKI/OMultiplexed I/O & Peripheral Pin SD_SCK (SPI)
53GNDGNDGround Reference Pin (GND)
54VSDIOI/OMultiplexed I/O & Peripheral Pin VSDIO (General)
55SD_CMD/PSELFI/OMultiplexed I/O & Peripheral Pin SD_CMD/PSELF (General)
56PWR_CC1I/OMultiplexed I/O & Peripheral Pin PWR_CC1 (General)
57PWR_CC2I/OMultiplexed I/O & Peripheral Pin PWR_CC2 (General)
58RESET#ISystem Enable & Hardware Reset (RESET#)
59PD_CTL1/GPIO1I/OMultiplexed I/O & Peripheral Pin PD_CTL1/GPIO1 (General)
60DVDDKPowerPower Supply Input (DVDDK — 3.3V / 5.0V Standard Logic)
61GNDGNDGround Reference Pin (GND)
62SRST/PWREN2#I/OMultiplexed I/O & Peripheral Pin SRST/PWREN2# (General)
63VIO33I/OMultiplexed I/O & Peripheral Pin VIO33 (General)
64TRST/PWREN3#I/OMultiplexed I/O & Peripheral Pin TRST/PWREN3# (General)
65TCK/PWREN4#I/OMultiplexed I/O & Peripheral Pin TCK/PWREN4# (General)
66TMS/PWREN5#I/OMultiplexed I/O & Peripheral Pin TMS/PWREN5# (General)
67TDO/PWREN6#I/OMultiplexed I/O & Peripheral Pin TDO/PWREN6# (General)
68TDI/PWREN7#I/OMultiplexed I/O & Peripheral Pin TDI/PWREN7# (General)
69EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 MDITP
I/O
Multiplexed I/O & Peripheral Pin MDITP (General)
Design note: Signal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH339W (WCH · QFN-68(8x8))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH339W (QFN-68(8x8)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH339W (QFN-68(8x8)) - 2. Standard Pinout (Top View)
True package pinout (69 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH339W (QFN-68(8x8)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH339W (QFN-68(8x8)) - 4. Package Dimensions (D×E×A)
QFN-68(8x8) · 8.00×8.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH339W (QFN-68(8x8)) - 5. Recommended Land Pattern
IPC-7351B Footprint (69 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH339W (QFN-68(8x8)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for CH339
P4 · p04_fig01EXACT PACKAGE
CH339W (QFN-68(8x8)) — 引脚号（同名引脚可参考） 引脚 名称 类型
引脚号（同名引脚可参考） 引脚 名称 类型
P1 · p01_fig011586×1344px
CH339W (QFN-68(8x8)) — 图1-1 系统框图
图1-1 系统框图
P3 · p03_fig011089×1269px
CH339W (QFN-68(8x8)) — 表1-1 功能对比 型号 功能 CH339W CH339F | TT 模式 MTT MTT USB 端口数 7 4 过流检测 独立或GANG GANG 模式 电源控制 独立或GANG GANG 模式 I/0 引脚配置 | 供电模式 √ × | 外部/内部EEPROM | 提供配置信息 √ √ | 定制配置信息 √ √ 上行口交换功能 √ × 隔离/延长功能 √ √ USB 网卡功能 √ √ USB 读卡器功能 √ √ USB 转JTAG 功能 √ × USB 转SPI 功能
表1-1 功能对比 型号 功能 CH339W CH339F | TT 模式 MTT MTT USB 端口数 7 4 过流检测 独立或GANG GANG 模式 电源控制 独立或GANG GANG 模式 I/0 引脚配置 | 供电模式 √ × | 外部/内部EEPROM | 提供配置信息 √ √ | 定制配置信息 √ √ 上行口交换功能 √ × 隔离/延长功能 √ √ USB 网卡功能 √ √ USB 读卡器功能 √ √ USB 转JTAG 功能 √ × USB 转SPI 功能
P9 · p09_fig011523×599px
CH339W (QFN-68(8x8)) — CH339F 提供两线I2C 接口与外部EEPROM 存储芯片通信，EEPROM 芯片地址为0，EEPROM 中存储有 自定义的厂商ID、产品ID、下行端口个数、下行端口的设备不可移除特性、USB 字符串描述符和功 能配置等信息。
CH339F 提供两线I2C 接口与外部EEPROM 存储芯片通信，EEPROM 芯片地址为0，EEPROM 中存储有 自定义的厂商ID、产品ID、下行端口个数、下行端口的设备不可移除特性、USB 字符串描述符和功 能配置等信息。
P14 · p14_fig011201×596px
CH339W (QFN-68(8x8)) — 图5-5 肖特基二极管双向隔离VBUS和外部供电的示意图
图5-5 肖特基二极管双向隔离VBUS和外部供电的示意图
P14 · p14_fig021231×659px
CH339W (QFN-68(8x8)) — 5.7 USB 转以太网功能
5.7 USB 转以太网功能
P14 · p14_fig02P14
CH339W (QFN-68(8x8)) — Datasheet Page 14 (p14_fig02)
Datasheet Page 14 (p14_fig02)
P19 · p19_fig011649×1085px
CH339W (QFN-68(8x8)) — 图8-1 HUB+USB 读卡器+USB 网卡应用参考电路图 C3 VSDIO OVCUR# 17 PWREN# 18 SD_D3 19 SD_D2 20 SD_D1 21 SD_D0 22 SD_SCK/CFG1 23 VSDIO 24
图8-1 HUB+USB 读卡器+USB 网卡应用参考电路图 C3 VSDIO OVCUR# 17 PWREN# 18 SD_D3 19 SD_D2 20 SD_D1 21 SD_D0 22 SD_SCK/CFG1 23 VSDIO 24
P19 · p19_fig021716×1479px
CH339W (QFN-68(8x8)) — UD+ 3
UD+ 3
P21 · p21_fig011713×2503px
CH339W (QFN-68(8x8)) — 图8-2 PD HUB+USB 读卡器+USB 网卡+USB 转多种接口应用参考电路图
图8-2 PD HUB+USB 读卡器+USB 网卡+USB 转多种接口应用参考电路图

Technical Specifications & Part Details (CH339W)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH339W (QFN-68(8x8)) is a 68-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, SDIO, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-68(8x8))
Pin Count & Lead PitchN / e
68 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, SDIO, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol69 auto-grouped pins
OK
IPC-7351B Land Pattern69 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteEPAD 5.50×5.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-68(8x8))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.80 mm
Pins / Total PadsTopology
69P / 69Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-68(8x8)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH339W (QFN-68(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH339W (QFN-68(8x8))?

Manufactured by WCH, the CH339W is housed in a QFN-68(8x8) package with 69 pins and a 0.40 mm lead pitch. Key pins include: 1 (MDITP: Multiplexed I/O & Peripheral Pin MDITP (General)), 2 (MDITN: Multiplexed I/O & Peripheral Pin MDITN (General)), 3 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)), 4 (MDIRP: Multiplexed I/O & Peripheral Pin MDIRP (General)), 5 (MDIRN: Multiplexed I/O & Peripheral Pin MDIRN (General)), 6 (GND: Ground Reference Pin (GND)).

What are the IPC-7351B PCB Footprint dimensions for CH339W?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH339W (QFN-68(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.40 mm, and 69 copper pads plus a central exposed thermal pad (EPAD) of 5.50 × 5.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH339W?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH339W (WCH, QFN-68(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (69 pins) & CH339 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MDITPDigital_IOSignal terminal MDITP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITP. Supported peripheral buses: General.
2MDITNDigital_IOSignal terminal MDITN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDITN. Supported peripheral buses: General.
3VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
4MDIRPDigital_IOSignal terminal MDIRP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRP. Supported peripheral buses: General.
5MDIRNDigital_IOSignal terminal MDIRN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MDIRN. Supported peripheral buses: General.
6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
7NCNo_ConnectNo Connect (Leave Floating)
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10DP7Digital_IOSignal terminal DP7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DP7. Supported peripheral buses: General.
11VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
16XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
17AVDDKPower_InPrimary positive power supply input (AVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24IO13Digital_IOGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14Digital_IOGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26IO21Digital_IOGPIO21 / RTC_GPIO21
27IO47Digital_IOGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28IO33Digital_IOGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29IO29Digital_IOGeneral Purpose Digital I/O Pin IO29
30VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31LED_ACT/CFG0Digital_IOSignal terminal LED_ACT/CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_ACT/CFG0. Supported peripheral buses: General.
32RXD/OVCUR3#Digital_IOSignal terminal RXD/OVCUR3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD/OVCUR3#. Supported peripheral buses: UART.
33TXD/OVCUR2#Digital_IOSignal terminal TXD/OVCUR2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD/OVCUR2#. Supported peripheral buses: UART.
34OVCUR1#Digital_IOSignal terminal OVCUR1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OVCUR1#. Supported peripheral buses: General.
35LED_LINK/CFG1Digital_IOSignal terminal LED_LINK/CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED_LINK/CFG1. Supported peripheral buses: General.
36PD_CTL3/GPIO3Digital_IOSignal terminal PD_CTL3/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD_CTL3/GPIO3. Supported peripheral buses: General.
37PD_CIL2/GPIO2Digital_IOSignal terminal PD_CIL2/GPIO2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD_CIL2/GPIO2. Supported peripheral buses: General.
38SDA/SMBDAT/CTSDigital_IOSignal terminal SDA/SMBDAT/CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA/SMBDAT/CTS. Supported peripheral buses: UART, I2C.
39SCL/SMBCLK/RTSDigital_IOSignal terminal SCL/SMBCLK/RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL/SMBCLK/RTS. Supported peripheral buses: UART, I2C.
40VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
41PWREN1#Digital_IOSignal terminal PWREN1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWREN1#. Supported peripheral buses: General.
42SCK/OVCUR4#Digital_IOSignal terminal SCK/OVCUR4# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/OVCUR4#. Supported peripheral buses: SPI.
43SCS/OVCUR5#Digital_IOSignal terminal SCS/OVCUR5# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS/OVCUR5#. Supported peripheral buses: General.
44MOSI/OVCUR6#Digital_IOSignal terminal MOSI/OVCUR6# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOSI/OVCUR6#. Supported peripheral buses: SPI.
45MISO/OVCUR7#Digital_IOSignal terminal MISO/OVCUR7# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MISO/OVCUR7#. Supported peripheral buses: SPI.
46SDVCC_EN/CFG2Power_InPrimary positive power supply input (SDVCC_EN/CFG2) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
47HUB_CCDigital_IOSignal terminal HUB_CC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HUB_CC. Supported peripheral buses: General.
48SD_D3Digital_IOSignal terminal SD_D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D3. Supported peripheral buses: General.
49SD_D2Digital_IOSignal terminal SD_D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D2. Supported peripheral buses: General.
50SD_D1Digital_IOSignal terminal SD_D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D1. Supported peripheral buses: General.
51SD_D0Digital_IOSignal terminal SD_D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D0. Supported peripheral buses: General.
52SD_SCKDigital_IOSignal terminal SD_SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_SCK. Supported peripheral buses: SPI.
53GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
54VSDIODigital_IOSignal terminal VSDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSDIO. Supported peripheral buses: General.
55SD_CMD/PSELFDigital_IOSignal terminal SD_CMD/PSELF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CMD/PSELF. Supported peripheral buses: General.
56PWR_CC1Digital_IOSignal terminal PWR_CC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWR_CC1. Supported peripheral buses: General.
57PWR_CC2Digital_IOSignal terminal PWR_CC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWR_CC2. Supported peripheral buses: General.
58RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
59PD_CTL1/GPIO1Digital_IOSignal terminal PD_CTL1/GPIO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD_CTL1/GPIO1. Supported peripheral buses: General.
60DVDDKPower_InPrimary positive power supply input (DVDDK) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
61GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
62SRST/PWREN2#Digital_IOSignal terminal SRST/PWREN2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SRST/PWREN2#. Supported peripheral buses: General.
63VIO33Digital_IOSignal terminal VIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VIO33. Supported peripheral buses: General.
64TRST/PWREN3#Digital_IOSignal terminal TRST/PWREN3# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TRST/PWREN3#. Supported peripheral buses: General.
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