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PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC24FJ128GA010-I/PT

MICROCHIPID: C24799TQFP-100(12x12) · 100 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC24FJ128GA010-I/PT (TQFP-100(12x12))1ST2ST3ST4ST5ST6－7ST8ST9T5CK/RC410PMA5/SCK2/CN11ST12ST13ST14ST15ANA16ANA17ST18ST19－20－21ST22ST23ST24－25PGD1/EMUD1/A26IO2127ST28ST29－30ST31ST32－33DIG34ST35－36I2C37I2C38－39ST40ST41－42－43ST44ST45ST46ST47ANA48ST49ST50ST100PMD4/RE499PMD3/RE398PMD2/RE297RG1396RG1295RG1494PMD1/RE193PMD0/RE092RA791RA690RG089RG188RF187RF086ENVREG85VCAP/VDDCORE84CN16/RD783CN15/RD682PMRD/CN14/RD81PMWR/OC5/CN180CN19/RD1379IC5/RD1278PMBE/OC4/RD377OC3/RD276OC2/RD175VSS74SOSCO/T1CK/C73SOSCI/CN1/RC72OC1/RD071IC4/PMCS1/RD70IC3/PMCS2/RD69IC2/RD968IC1/RTCC/RD867INT4/RA1566INT3/RA1465VSS64ST63ST62ST61ST60ST59ST58ST57ST56－55ST54ST53ST52ST51STGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=12.00mm · Pitch e=0.40mmD=12.00mm-11-9-7-5-3-113579111197531-1-3-5-7-9-11mm
3. 3D CAD MODEL
Package Body: 12.00mm × 12.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1STI/OMultiplexed I/O & Peripheral Pin ST (General)
2STI/OMultiplexed I/O & Peripheral Pin ST (General)
3STI/OMultiplexed I/O & Peripheral Pin ST (General)
4STI/OMultiplexed I/O & Peripheral Pin ST (SPI)
5STI/OMultiplexed I/O & Peripheral Pin ST (General)
6－I/OMultiplexed I/O & Peripheral Pin － (General)
7STI/OMultiplexed I/O & Peripheral Pin ST (General)
8STI/OMultiplexed I/O & Peripheral Pin ST (General)
9T5CK/RC4I/OMultiplexed I/O & Peripheral Pin T5CK/RC4 (General)
10PMA5/SCK2/CN8/RG6I/OMultiplexed I/O & Peripheral Pin PMA5/SCK2/CN8/RG6 (SPI)
11STI/OMultiplexed I/O & Peripheral Pin ST (General)
12STI/OMultiplexed I/O & Peripheral Pin ST (General)
13STI/OMultiplexed I/O & Peripheral Pin ST (General)
14STI/OMultiplexed I/O & Peripheral Pin ST (General)
15ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
16ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
17STI/OMultiplexed I/O & Peripheral Pin ST (General)
18STI/OMultiplexed I/O & Peripheral Pin ST (General)
19－I/OMultiplexed I/O & Peripheral Pin － (General)
20－I/OMultiplexed I/O & Peripheral Pin － (General)
21STI/OMultiplexed I/O & Peripheral Pin ST (General)
22STI/OMultiplexed I/O & Peripheral Pin ST (General)
23STI/OMultiplexed I/O & Peripheral Pin ST (General)
24－I/OMultiplexed I/O & Peripheral Pin － (General)
25PGD1/EMUD1/AN0/CN2/RB0I/OMultiplexed I/O & Peripheral Pin PGD1/EMUD1/AN0/CN2/RB0 (General)
26IO21I/OGPIO21 / RTC_GPIO21
27STI/OMultiplexed I/O & Peripheral Pin ST (General)
28STI/OMultiplexed I/O & Peripheral Pin ST (General)
29－I/OMultiplexed I/O & Peripheral Pin － (General)
30STI/OMultiplexed I/O & Peripheral Pin ST (General)
31STI/OMultiplexed I/O & Peripheral Pin ST (General)
32－I/OMultiplexed I/O & Peripheral Pin － (General)
33DIGI/OMultiplexed I/O & Peripheral Pin DIG (General)
34STI/OMultiplexed I/O & Peripheral Pin ST (General)
35－I/OMultiplexed I/O & Peripheral Pin － (General)
36I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
37I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
38－I/OMultiplexed I/O & Peripheral Pin － (General)
39STI/OMultiplexed I/O & Peripheral Pin ST (General)
40STI/OMultiplexed I/O & Peripheral Pin ST (General)
41－I/OMultiplexed I/O & Peripheral Pin － (General)
42－I/OMultiplexed I/O & Peripheral Pin － (RTC/CLK)
43STI/OMultiplexed I/O & Peripheral Pin ST (General)
44STI/OMultiplexed I/O & Peripheral Pin ST (General)
45STI/OMultiplexed I/O & Peripheral Pin ST (General)
46STI/OMultiplexed I/O & Peripheral Pin ST (General)
47ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
48STI/OMultiplexed I/O & Peripheral Pin ST (General)
49STI/OMultiplexed I/O & Peripheral Pin ST (General)
50STI/OMultiplexed I/O & Peripheral Pin ST (General)
51STI/OMultiplexed I/O & Peripheral Pin ST (General)
52STI/OMultiplexed I/O & Peripheral Pin ST (General)
53STI/OMultiplexed I/O & Peripheral Pin ST (General)
54STI/OMultiplexed I/O & Peripheral Pin ST (General)
55STI/OMultiplexed I/O & Peripheral Pin ST (General)
56－I/OMultiplexed I/O & Peripheral Pin － (General)
57STI/OMultiplexed I/O & Peripheral Pin ST (General)
58STI/OMultiplexed I/O & Peripheral Pin ST (General)
59STI/OMultiplexed I/O & Peripheral Pin ST (General)
60STI/OMultiplexed I/O & Peripheral Pin ST (General)
61STI/OMultiplexed I/O & Peripheral Pin ST (General)
62STI/OMultiplexed I/O & Peripheral Pin ST (General)
63STI/OMultiplexed I/O & Peripheral Pin ST (General)
64STI/OMultiplexed I/O & Peripheral Pin ST (General)
65VSSGNDExposed Thermal & Ground Pad (VSS)
66INT3/RA14I/OMultiplexed I/O & Peripheral Pin INT3/RA14 (General)
67INT4/RA15I/OMultiplexed I/O & Peripheral Pin INT4/RA15 (General)
68IC1/RTCC/RD8I/OMultiplexed I/O & Peripheral Pin IC1/RTCC/RD8 (RTC/CLK)
69IC2/RD9I/OMultiplexed I/O & Peripheral Pin IC2/RD9 (General)
70IC3/PMCS2/RD10I/OMultiplexed I/O & Peripheral Pin IC3/PMCS2/RD10 (General)
71IC4/PMCS1/RD11I/OMultiplexed I/O & Peripheral Pin IC4/PMCS1/RD11 (General)
72OC1/RD0I/OMultiplexed I/O & Peripheral Pin OC1/RD0 (General)
73SOSCI/CN1/RC13I/OMultiplexed I/O & Peripheral Pin SOSCI/CN1/RC13 (General)
74SOSCO/T1CK/CN0/RC14I/OMultiplexed I/O & Peripheral Pin SOSCO/T1CK/CN0/RC14 (General)
75VSSGNDGround Reference Pin (VSS)
76OC2/RD1I/OMultiplexed I/O & Peripheral Pin OC2/RD1 (General)
77OC3/RD2I/OMultiplexed I/O & Peripheral Pin OC3/RD2 (General)
78PMBE/OC4/RD3I/OMultiplexed I/O & Peripheral Pin PMBE/OC4/RD3 (General)
79IC5/RD12I/OMultiplexed I/O & Peripheral Pin IC5/RD12 (General)
80CN19/RD13I/OMultiplexed I/O & Peripheral Pin CN19/RD13 (General)
81PMWR/OC5/CN13/RD4I/OMultiplexed I/O & Peripheral Pin PMWR/OC5/CN13/RD4 (General)
82PMRD/CN14/RD5I/OMultiplexed I/O & Peripheral Pin PMRD/CN14/RD5 (General)
83CN15/RD6I/OMultiplexed I/O & Peripheral Pin CN15/RD6 (General)
84CN16/RD7I/OMultiplexed I/O & Peripheral Pin CN16/RD7 (General)
85VCAP/VDDCOREPowerPower Supply Input (VCAP/VDDCORE — 3.3V / 5.0V Standard Logic)
86ENVREGI/OMultiplexed I/O & Peripheral Pin ENVREG (General)
87RF0I/OMultiplexed I/O & Peripheral Pin RF0 (General)
88RF1I/OMultiplexed I/O & Peripheral Pin RF1 (General)
89RG1I/OMultiplexed I/O & Peripheral Pin RG1 (General)
90RG0I/OMultiplexed I/O & Peripheral Pin RG0 (General)
91RA6I/OMultiplexed I/O & Peripheral Pin RA6 (General)
92RA7I/OMultiplexed I/O & Peripheral Pin RA7 (General)
93PMD0/RE0I/OMultiplexed I/O & Peripheral Pin PMD0/RE0 (General)
94PMD1/RE1I/OMultiplexed I/O & Peripheral Pin PMD1/RE1 (General)
95RG14I/OMultiplexed I/O & Peripheral Pin RG14 (General)
96RG12I/OMultiplexed I/O & Peripheral Pin RG12 (General)
97RG13I/OMultiplexed I/O & Peripheral Pin RG13 (General)
98PMD2/RE2I/OMultiplexed I/O & Peripheral Pin PMD2/RE2 (General)
99PMD3/RE3I/OMultiplexed I/O & Peripheral Pin PMD3/RE3 (General)
100PMD4/RE4I/OMultiplexed I/O & Peripheral Pin PMD4/RE4 (General)
PIN 1 ST
I/O
Multiplexed I/O & Peripheral Pin ST (General)
Design note: RE5
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC24FJ128GA010-I/PT (MICROCHIP · TQFP-100(12x12))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 4. Package Dimensions (D×E×A)
TQFP-100(12x12) · 12.00×12.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for PIC24FJ128GA
P2 · p02_fig011783×2636px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — DS39747E_CN 第2 页  2011 Microchip Technology Inc. | 提供本文档的中文版本仅为了便于理解。请勿忽视文档中包含 的英文部分，因为其中提供了有关Microchip 产品性能和使用 情况的有用信息。Microchip Technology Inc. 及其分公司和相 关公司、各级主管与员工及事务代理机构对译文中可能存在的 任何差错不承担任何责任。建议参考Microchip Technology Inc. 的英文原版文档。 | 商标 |
DS39747E_CN 第2 页  2011 Microchip Technology Inc. | 提供本文档的中文版本仅为了便于理解。请勿忽视文档中包含 的英文部分，因为其中提供了有关Microchip 产品性能和使用 情况的有用信息。Microchip Technology Inc. 及其分公司和相 关公司、各级主管与员工及事务代理机构对译文中可能存在的 任何差错不承担任何责任。建议参考Microchip Technology Inc. 的英文原版文档。 | 商标 |
P2 · p02_fig02785×283px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — DS39747E_CN 第2 页  2011 Microchip Technology Inc.
DS39747E_CN 第2 页  2011 Microchip Technology Inc.
P4 · p04_fig011657×1098px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 2 3 4 5 6 7 8 9 10 11 12 | 13 14 15 16 | 48 | 47 | 22 | 44 | 24 25 26 27 28 29 30 31 32 | PIC24FJXXGA006 | 1 | 46 | 45 | 23 | 43 | 42 | 41 | 40 | 39 | CN15/RD6 | PMRD/CN14/RD5 | PMWR/OC5/IC5/CN13/RD4 | PMBE/OC4/RD3 | OC3/RD2 | OC2/RD1 | PMD
2 3 4 5 6 7 8 9 10 11 12 | 13 14 15 16 | 48 | 47 | 22 | 44 | 24 25 26 27 28 29 30 31 32 | PIC24FJXXGA006 | 1 | 46 | 45 | 23 | 43 | 42 | 41 | 40 | 39 | CN15/RD6 | PMRD/CN14/RD5 | PMWR/OC5/IC5/CN13/RD4 | PMBE/OC4/RD3 | OC3/RD2 | OC2/RD1 | PMD
P12 · p12_fig011655×2335px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 图1-1： PIC24FJ128GA010 系列的通用框图
图1-1： PIC24FJ128GA010 系列的通用框图
P47 · p47_fig011779×635px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 闪存存储器的编程都是用表读和表写指令实现的，与使 用的方法无关。 这些指令允许器件在正常工作模式下通 过数据存储器直接读写程序存储空间。 24 位程序存储 器目标地址由TBLPAG<7:0> 和W 寄存器中的有效地址 （EA）组成，如图4-1 所示。
闪存存储器的编程都是用表读和表写指令实现的，与使 用的方法无关。 这些指令允许器件在正常工作模式下通 过数据存储器直接读写程序存储空间。 24 位程序存储 器目标地址由TBLPAG<7:0> 和W 寄存器中的有效地址 （EA）组成，如图4-1 所示。
P47 · p47_fig021387×783px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 图4-1： 表寄存器寻址
图4-1： 表寄存器寻址
P197 · p197_fig011780×815px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 注： 本数据手册总结了该系列PIC24F 器件的功 能。但它并不是一份无所不包的参考资料。 欲知更多信息，请参见《PIC24F 系列参考 手册》的第 33 章“编程和诊断” （DS39716A_CN） 。
注： 本数据手册总结了该系列PIC24F 器件的功 能。但它并不是一份无所不包的参考资料。 欲知更多信息，请参见《PIC24F 系列参考 手册》的第 33 章“编程和诊断” （DS39716A_CN） 。
P197 · p197_fig021327×580px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 要使用器件的在线调试功能，在设计中必须实现 MCLR、 VDD、 VSS、 PGCx、PGDx 和EMUDx/EMUCx 引脚对的正确连接。 此外，如果使能ICSP 功能，某些 资源将无法通用。 这些资源包括数据RAM 的前80 个字 节和两个I/O 引脚。
要使用器件的在线调试功能，在设计中必须实现 MCLR、 VDD、 VSS、 PGCx、PGDx 和EMUDx/EMUCx 引脚对的正确连接。 此外，如果使能ICSP 功能，某些 资源将无法通用。 这些资源包括数据RAM 的前80 个字 节和两个I/O 引脚。
P197 · p197_fig01P197
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — Datasheet Page 197 (p197_fig01)
Datasheet Page 197 (p197_fig01)
P226 · p226_fig011782×2364px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — 以下部分将介绍各种封装技术的细节。
以下部分将介绍各种封装技术的细节。
P227 · p227_fig011778×2173px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — PIC24FJ128GA010 系列
PIC24FJ128GA010 系列
P228 · p228_fig011778×2212px
PIC24FJ128GA010-I/PT (TQFP-100(12x12)) — PIC24FJ128GA010 系列
PIC24FJ128GA010 系列

Technical Specifications & Part Details (PIC24FJ128GA010-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC24FJ128GA010-I/PT (TQFP-100(12x12)) is a 100-pin standard electronic & interconnect component featuring a 12.00 × 12.00 × 1.20 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, PWM, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
12.00 × 12.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-100(12x12))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, PWM, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-100(12x12))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
12.00 × 12.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-100(12x12)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24FJ128GA010-I/PT (TQFP-100(12x12))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24FJ128GA010-I/PT (TQFP-100(12x12))?

Manufactured by MICROCHIP, the PIC24FJ128GA010-I/PT is housed in a TQFP-100(12x12) package with 100 pins and a 0.40 mm lead pitch. Key pins include: 1 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 2 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 3 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 4 (ST: Multiplexed I/O & Peripheral Pin ST (SPI)), 5 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 6 (－: Multiplexed I/O & Peripheral Pin － (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24FJ128GA010-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24FJ128GA010-I/PT (TQFP-100(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.40 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24FJ128GA010-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24FJ128GA010-I/PT (MICROCHIP, TQFP-100(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & PIC24FJ128GA Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
2STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
3STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
4STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: SPI.
5STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
6－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
7STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
8STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
9T5CK/RC4Digital_IOSignal terminal T5CK/RC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: T5CK/RC4. Supported peripheral buses: General.
10PMA5/SCK2/CN8/RG6Digital_IOSignal terminal PMA5/SCK2/CN8/RG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PMA5/SCK2/CN8/RG6. Supported peripheral buses: SPI.
11STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
12STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
13STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
14STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
15ANADigital_IOSignal terminal ANA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
16ANADigital_IOSignal terminal ANA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
17STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
18STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
19－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
20－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
21STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U2CTS. Supported peripheral buses: General.
22STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
23STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
24－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
25PGD1/EMUD1/AN0/CN2/RB0Digital_IOSignal terminal PGD1/EMUD1/AN0/CN2/RB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGD1/EMUD1/AN0/CN2/RB0. Supported peripheral buses: General.
26IO21Digital_IOGPIO21 / RTC_GPIO21
27STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
28STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
29－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U2RTS. Supported peripheral buses: General.
30STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
31STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
32－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
33DIGDigital_IOSignal terminal DIG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG. Supported peripheral buses: General.
34STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
35－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General.
36I2CDigital_IOSignal terminal I2C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
37I2CDigital_IOSignal terminal I2C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
38－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
39STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
40STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
41－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
42－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: RTC/CLK.
43STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U1CTS. Supported peripheral buses: General.
44STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
45STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
46STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
47ANADigital_IOSignal terminal ANA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
48STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
49STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
50STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
51STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
52STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
53STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
54STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
55STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
56－Digital_IOSignal terminal － (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: －. Supported peripheral buses: General.
57STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
58STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
59STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
60STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
61STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
62STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
63STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
64STDigital_IOSignal terminal ST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
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