ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H7R7Z8J6

STID: C24591626UFBGA-144(10x10) · 144 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H7R7Z8J6 (UFBGA-144(10x10))A1VSSA2PB8A3PB6A4PD7A5PD5A6PM12A7VDD50USBA8PD4A9PC10A10PA15A11PA9A12VSSB1VBATB2PC13B3PE1B4PB5B5PD6B6PM11B7VDD33USBB8PD3B9PD0B10PA13B11PA12B12PC8C1IOC1C2IOC2C3PB9C4PB7C5PB3C6BOOT0C7VSSC8PG1C9VSSC10PA14C11PA8C12PC6D1PE5D2VSSD3PE3D4VDDD5VSSD6VDDD7VSSD8PG0D9VDDD10PA10D11PC9D12PA15(JTDI)E1VSSSMPSE2PE6E3PE4E4VDDE5VCAP4E6PB4E7VSSE8VSSE9PA11E10PA14(JTCK/ SE11PA12E12PA13(JTMS/ SF1VLXSMPSF2VDDSMPSF3VFBSMPSF4NRSTF5VSSF6VDDLDOF7VDDLDOF8VCAP3F9VDDF10PA8F11PA10F12PA11M12VSSM11PD10M10PP7M9PP6M8PP5M7PO4M6PP3M5PP4M4PE8M3PC5M2PA6M1VSSL12PD13L11PD11L10PP1L9PO2L8PP0L7PO5L6PP2L5PB2L4PB0L3PC4L2PA4L1PA2K12PN8K11PD12K10VSSK9VDDXSPI1K8VSSK7VDDXSPI1K6PE7K5VDDXSPI1K4PA7K3VREFPK2PA3K1PA0J12PN5J11PN4J10VDDXSPI2J9VDDJ8PD8J7PO0J6PO1J5VDDJ4PA5J3VDDAJ2PA1J1PC2H12PC6H11PN7H10PB12H9PB14H8VCAP2H7VSSH6VCAP1H5VREFMH4VSSH3VSSAH2PC3H1PH1 - OSC OUG12PA9G11PC8G10PC9G9PC7G8VSSG7VDDLDOG6VDDLDOG5PC1G4VDDG3PC0G2PH0 - OSC ING1VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3F3G3H3J3K3L3M3A4B4C4D4E4F4G4H4J4K4L4M4A5B5C5D5E5F5G5H5J5K5L5M5A6B6C6D6E6F6G6H6J6K6L6M6A7B7C7D7E7F7G7H7J7K7L7M7A8B8C8D8E8F8G8H8J8K8L8M8A9B9C9D9E9F9G9H9J9K9L9M9A10B10C10D10E10F10G10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=10.00mm · Pitch e=0.80mmD=10.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSGNDGround Reference Pin (VSS)
A2PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
A4PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A5PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A6PM12I/OMultiplexed I/O & Peripheral Pin PM12 (General)
A7VDD50USBPowerPower Supply Input (VDD50USB — 3.3V VDD (Max 4.0V))
A8PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
A9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
A10PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A11PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
A12VSSGNDGround Reference Pin (VSS)
B1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
B3PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
B4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B5PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
B6PM11I/OMultiplexed I/O & Peripheral Pin PM11 (General)
B7VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
B9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
B10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
B11PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
B12PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
C1IOC1I/OGeneral Purpose Digital I/O Pin IOC1
C2IOC2I/OGeneral Purpose Digital I/O Pin IOC2
C3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (UART, SPI, I2C)
C4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
C5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
C6BOOT0IInput-Only Pin BOOT0 (General)
C7VSSGNDGround Reference Pin (VSS)
C8PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
C9VSSGNDGround Reference Pin (VSS)
C10PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
C11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
C12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
D1PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
D2VSSGNDGround Reference Pin (VSS)
D3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
D4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D5VSSGNDGround Reference Pin (VSS)
D6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D7VSSGNDGround Reference Pin (VSS)
D8PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
D9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
D12PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
E1VSSSMPSGNDGround Reference Pin (VSSSMPS)
E2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
E3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
E4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E5VCAP4I/OMultiplexed I/O & Peripheral Pin VCAP4 (General)
E6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
E7VSSGNDGround Reference Pin (VSS)
E8VSSGNDGround Reference Pin (VSS)
E9PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
E10PA14(JTCK/ SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JTCK/ SWCLK) (SWD/JTAG)
E11PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI)
E12PA13(JTMS/ SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JTMS/ SWDIO) (SWD/JTAG)
F1VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
F2VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
F3VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
F4NRSTISystem Enable & Hardware Reset (NRST)
F5VSSGNDGround Reference Pin (VSS)
F6VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
F7VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
F8VCAP3I/OMultiplexed I/O & Peripheral Pin VCAP3 (General)
F9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
F11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
F12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
G1VSSGNDGround Reference Pin (VSS)
G2PH0 - OSC IN(PH_ 0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC IN(PH_ 0) (RTC/CLK)
G3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
G4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G5PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC)
G6VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
G7VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
G8VSSGNDGround Reference Pin (VSS)
G9PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
G10PC9I/OMultiplexed I/O & Peripheral Pin PC9 (UART, I2C, RTC/CLK)
G11PC8I/OMultiplexed I/O & Peripheral Pin PC8 (I2C)
G12PA9I/OMultiplexed I/O & Peripheral Pin PA9 (SPI, I2C, PWM)
H1PH1 - OSC OUT(_ PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(_ PH1) (RTC/CLK)
H2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC, PWM)
H3VSSAGNDGround Reference Pin (VSSA)
H4VSSGNDGround Reference Pin (VSS)
H5VREFMAnalogMultiplexed I/O & Peripheral Pin VREFM (General)
H6VCAP1I/OMultiplexed I/O & Peripheral Pin VCAP1 (General)
H7VSSGNDGround Reference Pin (VSS)
H8VCAP2I/OMultiplexed I/O & Peripheral Pin VCAP2 (General)
H9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
H10PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
H11PN7I/OMultiplexed I/O & Peripheral Pin PN7 (General)
H12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
J1PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC, PWM)
J2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
J3VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
J4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
J5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J6PO1I/OMultiplexed I/O & Peripheral Pin PO1 (General)
J7PO0I/OMultiplexed I/O & Peripheral Pin PO0 (General)
J8PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
J9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J10VDDXSPI2PowerPower Supply Input (VDDXSPI2 — 3.3V VDD (Max 4.0V))
J11PN4I/OMultiplexed I/O & Peripheral Pin PN4 (General)
J12PN5I/OMultiplexed I/O & Peripheral Pin PN5 (General)
K1PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
K2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, SPI, ADC, PWM)
K3VREFPAnalogMultiplexed I/O & Peripheral Pin VREFP (General)
K4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
K5VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
K6PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
K7VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
K8VSSGNDGround Reference Pin (VSS)
K9VDDXSPI1PowerPower Supply Input (VDDXSPI1 — 3.3V VDD (Max 4.0V))
K10VSSGNDGround Reference Pin (VSS)
K11PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
K12PN8I/OMultiplexed I/O & Peripheral Pin PN8 (General)
L1PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
L2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
L3PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
L4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
L5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, RTC/CLK)
L6PP2I/OMultiplexed I/O & Peripheral Pin PP2 (General)
L7PO5I/OMultiplexed I/O & Peripheral Pin PO5 (General)
L8PP0I/OMultiplexed I/O & Peripheral Pin PP0 (General)
L9PO2I/OMultiplexed I/O & Peripheral Pin PO2 (General)
L10PP1I/OMultiplexed I/O & Peripheral Pin PP1 (General)
L11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART)
L12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (SPI)
M1VSSGNDGround Reference Pin (VSS)
M2PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
M3PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
M4PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
M5PP4I/OMultiplexed I/O & Peripheral Pin PP4 (General)
M6PP3I/OMultiplexed I/O & Peripheral Pin PP3 (General)
M7PO4I/OMultiplexed I/O & Peripheral Pin PO4 (General)
M8PP5I/OMultiplexed I/O & Peripheral Pin PP5 (General)
M9PP6I/OMultiplexed I/O & Peripheral Pin PP6 (General)
M10PP7I/OMultiplexed I/O & Peripheral Pin PP7 (General)
M11PD10I/OMultiplexed I/O & Peripheral Pin PD10 (SPI, PWM)
M12VSSGNDGround Reference Pin (VSS)
PIN A1 VSS
GND
Ground Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H7R7Z8J6 (ST · UFBGA-144(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 4. Package Dimensions (D×E×A)
UFBGA-144(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H7R7Z8J6 (UFBGA-144(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32H7R3Z8J / STM32H7R7Z8J / STM32H7R3I8K
P74 · p74_fig01EXACT PACKAGE
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 7. UFBGA144 SMPS pinout(a)
Figure 7. UFBGA144 SMPS pinout(a)
P76 · p76_fig01EXACT PACKAGE
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 9. UFBGA144 GFx with SMPS pinout(a)
Figure 9. UFBGA144 GFx with SMPS pinout(a)
P293 · p293_fig01EXACT PACKAGE
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 87. UFBGA144 - Outline
Figure 87. UFBGA144 - Outline
P294 · p294_fig01EXACT PACKAGE
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 88. UFBGA144 - Recommended footprint
Figure 88. UFBGA144 - Recommended footprint
P1 · p01_fig01881×841px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — • 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
• 64 Kbytes of user flash memory that can be used for user code and/or external memory configuration.
P73 · p73_fig011751×1342px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 6. TFBGA100 SMPS pinout(a)
Figure 6. TFBGA100 SMPS pinout(a)
P74 · p74_fig01P74
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Datasheet Page 74 (p74_fig01)
Datasheet Page 74 (p74_fig01)
P147 · p147_fig011619×2259px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 23. Power supply scheme
Figure 23. Power supply scheme
P147 · p147_fig01P147
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Datasheet Page 147 (p147_fig01)
Datasheet Page 147 (p147_fig01)
P188 · p188_fig011546×500px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 35. Typical application with an 8 MHz crystal
Figure 35. Typical application with an 8 MHz crystal
P189 · p189_fig011546×516px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 36. Typical application with a 32.768 kHz crystal
Figure 36. Typical application with a 32.768 kHz crystal
P288 · p288_fig011546×1290px
STM32H7R7Z8J6 (UFBGA-144(10x10)) — Figure 84. TFBGA100 - Recommended footprint
Figure 84. TFBGA100 - Recommended footprint
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32H7R7Z8J6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H7R7Z8J6 (UFBGA-144(10x10)) is a 144-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 0.53 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
600 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
61 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-144(10x10))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, SDIO, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-144(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-144(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H7R7Z8J6 (UFBGA-144(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H7R7Z8J6 (UFBGA-144(10x10))?

Manufactured by ST, the STM32H7R7Z8J6 is housed in a UFBGA-144(10x10) package with 144 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A3 (PB6: Multiplexed I/O & Peripheral Pin PB6 (General)), A4 (PD7: Multiplexed I/O & Peripheral Pin PD7 (General)), A5 (PD5: Multiplexed I/O & Peripheral Pin PD5 (General)), A6 (PM12: Multiplexed I/O & Peripheral Pin PM12 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H7R7Z8J6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7R7Z8J6 (UFBGA-144(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7R7Z8J6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7R7Z8J6 (ST, UFBGA-144(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32H7R3Z8J / STM32H7R7Z8J / STM32H7R3I8K Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A2PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
A4PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A5PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A6PM12Digital_IOSignal terminal PM12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM12. Supported peripheral buses: General.
A7VDD50USBPower_InPrimary positive power supply input (VDD50USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A8PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
A9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
A10PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A11PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
A12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
B3PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
B4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B5PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
B6PM11Digital_IOSignal terminal PM11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PM11. Supported peripheral buses: General.
B7VDD33USBPower_InPrimary positive power supply input (VDD33USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
B9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
B10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
B11PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
B12PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
C1IOC1Digital_IOGeneral Purpose Digital I/O Pin IOC1
C2IOC2Digital_IOGeneral Purpose Digital I/O Pin IOC2
C3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
C4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
C5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
C6BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
C7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C8PG1Digital_IOSignal terminal PG1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General.
C9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C10PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
C12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
D1PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO_SAI1SCKA. Supported peripheral buses: SPI.
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
D4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D8PG0Digital_IOSignal terminal PG0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General.
D9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
D12PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS, SPI6_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
E1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
E2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
E3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS_SAI1FSA. Supported peripheral buses: SPI.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VCAP4Digital_IOSignal terminal VCAP4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP4. Supported peripheral buses: General.
E6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
E10PA14(JTCK/ SWCLK)Digital_IOSignal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCK/ SWCLK). Supported peripheral buses: SWD/JTAG.
E11PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
E12PA13(JTMS/ SWDIO)Digital_IOSignal terminal PA13(JTMS/ SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS/ SWDIO). Supported peripheral buses: SWD/JTAG.
F1VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
F2VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F3VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
F4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
ExplorePartsPackagesMFRsUpload