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C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) — Symbol, Footprint IPC-7351B & 3D STEP Model

C23172780

SemiconductorQFN-48_L7.0-W7.0-P0.50-TL-EP5.6 · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)1VBAT2PC133PC14-OSC32_I4PC15-OSC32_O5PH0-OSC_IN6PH1-OSC_OUT7NRST8VSSA9VDDA10PA011PA112PA213PA314PA415PA516PA617PA718PB019PB120PB221PB1022VCAP23VSS24VDD25PB1249EP48VDD47VSS46VCAP45PB844BOOT043PB742PB641PB540PB439PB338PA1537PA1436VDD35VSS34PA1333PA1232PA1131PA1030PA929PA828PB1527PB1426PB13Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
3PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
4PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
5PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
6PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8VSSAGNDGround Reference Pin (VSSA)
9VDDAPowerPower Supply Input (VDDA — 3.3V / 5.0V Standard Logic)
10PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
11PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
12PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
13PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
14PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
16PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
17PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
18PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
20PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
21PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
22VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
23VSSGNDGround Reference Pin (VSS)
24VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
29PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
30PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
31PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
32PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
33PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
34PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
35VSSGNDGround Reference Pin (VSS)
36VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
37PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
38PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
39PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
40PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
41PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
42PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
43PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
44BOOT0IInput-Only Pin BOOT0 (General)
45PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
46VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
47VSSGNDGround Reference Pin (VSS)
48VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
49EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C23172780 (Semiconductor · QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 4. Package Dimensions (D×E×A)
QFN-48_L7.0-W7.0-P0.50-TL-EP5.6 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C23172780)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-48_L7.0-W7.0-P0.50-TL-EP5.6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6)?

Manufactured by Semiconductor, the C23172780 is housed in a QFN-48_L7.0-W7.0-P0.50-TL-EP5.6 package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (PC14-OSC32_IN: Multiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)), 4 (PC15-OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)), 5 (PH0-OSC_IN: Multiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)), 6 (PH1-OSC_OUT: Multiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for C23172780?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C23172780 (QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C23172780?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C23172780 (Semiconductor, QFN-48_L7.0-W7.0-P0.50-TL-EP5.6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32H533 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
3PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
4PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
5PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
6PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
9VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
10PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
11PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
12PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
13PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
14PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
15PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
16PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
17PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
18PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
19PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
20PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
21PB10Digital_IOSignal terminal PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
22VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
23VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25PB12Digital_IOSignal terminal PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB14Digital_IOSignal terminal PB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
28PB15Digital_IOSignal terminal PB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
29PA8Digital_IOSignal terminal PA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
30PA9Digital_IOSignal terminal PA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
31PA10Digital_IOSignal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
32PA11Digital_IOSignal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
33PA12Digital_IOSignal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
34PA13Digital_IOSignal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
35VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
36VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37PA14Digital_IOSignal terminal PA14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
38PA15Digital_IOSignal terminal PA15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
39PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
40PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
41PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
42PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
43PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
44BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
45PB8Digital_IOSignal terminal PB8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
46VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
47VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
49EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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