ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32U5G9VJT6Q (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32U5G9VJT6Q

STID: C22445370LQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32U5G9VJT6Q (LQFP-100(14x14))1PE22PE33PE44PE55VDDDSI6VDD11DSI7DSI_D0P8DSI_D0N9VSSDSI10VSS11VDD12PH0 OSC IN(P13PH1OSC OUT(P14NRST15PC016PC117PC218PC319VSSA20VREF -21VREF+22VDDA23PA024PA125PA226PA327VSS28VDD29PA430PA531PA632PA733PC434PC535PB036PB137PB238PE739PE840PE941PE1042PE1143PE1244PE1345PE1446PE1547PB1048VCAP49VSS50VDD100VDD99VSS98VDD1197PB996PB895PH3-BOOT094PB793PB692PB591PB490PB389VDD88PD587PD486PD385PD284PD183PD082PC1281PC1180PC1079PA1578PA1477VSS76VDD75VDDUSB74PA1373PA1272PA1171PA1070PA969PA868PI367PI266VDD65VSS64PI163PI062PH1561PH1460VDD59VSS58PH1357PH1256PH1155PD854PB1553PB1452PB1351PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (UART)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (UART)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
5VDDDSIPowerPower Supply Input (VDDDSI — 3.3V VDD (Max 4.0V))
6VDD11DSIPowerPower Supply Input (VDD11DSI — 3.3V VDD (Max 4.0V))
7DSI_D0PI/OMultiplexed I/O & Peripheral Pin DSI_D0P (General)
8DSI_D0NI/OMultiplexed I/O & Peripheral Pin DSI_D0N (General)
9VSSDSIGNDGround Reference Pin (VSSDSI)
10VSSGNDGround Reference Pin (VSS)
11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
12PH0 OSC IN(PH0) -_I/OMultiplexed I/O & Peripheral Pin PH0 OSC IN(PH0) -_ (RTC/CLK)
13PH1OSC OUT(PH1) -_I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT(PH1) -_ (RTC/CLK)
14NRSTISystem Enable & Hardware Reset (NRST)
15PC0I/OMultiplexed I/O & Peripheral Pin PC0 (SPI, I2C, ADC)
16PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC)
17PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, SPI, ADC)
18PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
19VSSAGNDGround Reference Pin (VSSA)
20VREF -AnalogMultiplexed I/O & Peripheral Pin VREF - (General)
21VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
22VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
23PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
24PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, ADC, PWM)
25PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
26PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
27VSSGNDGround Reference Pin (VSS)
28VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
29PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC)
30PA5I/OMultiplexed I/O & Peripheral Pin PA5 (UART, SPI, ADC, DAC)
31PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
32PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, I2C, ADC)
33PC4I/OMultiplexed I/O & Peripheral Pin PC4 (I2C, ADC)
34PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
35PB0I/OMultiplexed I/O & Peripheral Pin PB0 (SPI, ADC, PWM)
36PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
37PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, ADC, PWM, RTC/CLK)
38PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
39PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
40PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
41PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
42PE11I/OMultiplexed I/O & Peripheral Pin PE11 (SPI)
43PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI)
44PE13I/OMultiplexed I/O & Peripheral Pin PE13 (SPI)
45PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
46PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
47PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C)
48VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
49VSSGNDExposed Thermal & Ground Pad (VSS)
50VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
51PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
52PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI)
53PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C)
54PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
55PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
56PH11I/OMultiplexed I/O & Peripheral Pin PH11 (General)
57PH12I/OMultiplexed I/O & Peripheral Pin PH12 (PWM)
58PH13I/OMultiplexed I/O & Peripheral Pin PH13 (General)
59VSSGNDGround Reference Pin (VSS)
60VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
61PH14I/OMultiplexed I/O & Peripheral Pin PH14 (General)
62PH15I/OMultiplexed I/O & Peripheral Pin PH15 (General)
63PI0I/OMultiplexed I/O & Peripheral Pin PI0 (General)
64PI1I/OMultiplexed I/O & Peripheral Pin PI1 (SPI)
65VSSGNDExposed Thermal & Ground Pad (VSS)
66VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
67PI2I/OMultiplexed I/O & Peripheral Pin PI2 (PWM)
68PI3I/OMultiplexed I/O & Peripheral Pin PI3 (General)
69PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
70PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
71PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
72PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
73PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
74PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
75VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
76VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
77VSSGNDGround Reference Pin (VSS)
78PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
79PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
80PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
81PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
82PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
83PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
84PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
85PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
86PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
87PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
88PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
89VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
90PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
91PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
92PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
93PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
94PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
95PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
96PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
97PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
98VDD11PowerPower Supply Input (VDD11 — 3.3V VDD (Max 4.0V))
99VSSGNDGround Reference Pin (VSS)
100VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (UART)
Design note: Alt: TRACECLK TIM3 ETR SAI1 CK1 ,_ ,_ , USART6 CK LCD R0_TSCG7IO1 ,_ ,__ , LPGPIO1 P14 FMC A23_SAI1MCLKA ,_ ,__ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32U5G9VJT6Q (ST · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32U5G9VJT6Q (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32U5G9VJT6Q (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32U5G9VJT6Q (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32U5G9VJT6Q (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32U5G9VJT6Q (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32U5G9VJT6Q (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32U5G9VJT
P98 · p98_fig01EXACT PACKAGE
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 6. LQFP100_SMPS pinout
Figure 6. LQFP100_SMPS pinout
P99 · p99_fig01EXACT PACKAGE
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 7. LQFP100 pinout PH3-BOOT0 92
Figure 7. LQFP100 pinout PH3-BOOT0 92
P100 · p100_fig01EXACT PACKAGE
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 8. LQFP100_DSI_SMPS pinout PH3-BOOT0 97
Figure 8. LQFP100_DSI_SMPS pinout PH3-BOOT0 97
P335 · p335_fig01EXACT PACKAGE
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 83. LQFP100 - Outline(15)
Figure 83. LQFP100 - Outline(15)
P1 · p01_fig01881×398px
STM32U5G9VJT6Q (LQFP-100(14x14)) — March 2025 DS14102 Rev 3 1/353
March 2025 DS14102 Rev 3 1/353
P2 · p02_fig01893×353px
STM32U5G9VJT6Q (LQFP-100(14x14)) — • 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers, and 2 watchdogs
• 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), 2 SysTick timers, and 2 watchdogs
P98 · p98_fig01P98
STM32U5G9VJT6Q (LQFP-100(14x14)) — Datasheet Page 98 (p98_fig01)
Datasheet Page 98 (p98_fig01)
P160 · p160_fig011546×1835px
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 15. STM32U5Gxxx power supply scheme (without SMPS)
Figure 15. STM32U5Gxxx power supply scheme (without SMPS)
P160 · p160_fig01P160
STM32U5G9VJT6Q (LQFP-100(14x14)) — Datasheet Page 160 (p160_fig01)
Datasheet Page 160 (p160_fig01)
P161 · p161_fig011546×2197px
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 16. STM32U5GxxxxxQ power supply scheme (with SMPS)
Figure 16. STM32U5GxxxxxQ power supply scheme (with SMPS)
P229 · p229_fig011547×698px
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 23. Typical application with an 8 MHz crystal
Figure 23. Typical application with an 8 MHz crystal
P259 · p259_fig011751×982px
STM32U5G9VJT6Q (LQFP-100(14x14)) — Figure 30. ADC accuracy characteristics
Figure 30. ADC accuracy characteristics
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32U5G9VJT6Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32U5G9VJT6Q (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
160 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
43 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.55 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.55mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32U5G9VJT6Q (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32U5G9VJT6Q (LQFP-100(14x14))?

Manufactured by ST, the STM32U5G9VJT6Q is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (UART)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (UART)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), 5 (VDDDSI: Power Supply Input (VDDDSI — 3.3V VDD (Max 4.0V))), 6 (VDD11DSI: Power Supply Input (VDD11DSI — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32U5G9VJT6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32U5G9VJT6Q (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32U5G9VJT6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32U5G9VJT6Q (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32U5G9VJT Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: UART.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: UART.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: SPI.
5VDDDSIPower_InPrimary positive power supply input (VDDDSI) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6VDD11DSIPower_InPrimary positive power supply input (VDD11DSI) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7DSI_D0PDigital_IOSignal terminal DSI_D0P (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D0P. Supported peripheral buses: General.
8DSI_D0NDigital_IOSignal terminal DSI_D0N (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: DSI_D0N. Supported peripheral buses: General.
9VSSDSIGND0V electrical ground return terminal (VSSDSI) for internal core logic, I/O drivers, and analog sub-blocks.
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
12PH0 OSC IN(PH0) -_Digital_IOSignal terminal PH0 OSC IN(PH0) -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 OSC IN(PH0) -_. Supported peripheral buses: RTC/CLK.
13PH1OSC OUT(PH1) -_Digital_IOSignal terminal PH1OSC OUT(PH1) -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1OSC OUT(PH1) -_. Supported peripheral buses: RTC/CLK.
14NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
15PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI2_RDY. Supported peripheral buses: SPI, I2C, ADC.
16PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, I2C3_SDA. Supported peripheral buses: SPI, I2C, ADC.
17PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISOMDF1CCK1. Supported peripheral buses: UART, SPI, ADC.
18PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSIUSART6TX. Supported peripheral buses: SPI, ADC.
19VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
20VREF -AnalogSignal terminal VREF - (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF -. Supported peripheral buses: General.
21VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
22VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
23PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_RDY. Supported peripheral buses: UART, SPI, ADC, PWM.
24PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, I2C, ADC, PWM.
25PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
26PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
27VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
28VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
29PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSSUSART2CK. Supported peripheral buses: SPI, ADC, DAC.
30PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: UART, SPI, ADC, DAC.
31PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
32PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MOSI. Supported peripheral buses: UART, SPI, I2C, ADC.
33PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: I2C, ADC.
34PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
35PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSUSART3CK. Supported peripheral buses: SPI, ADC, PWM.
36PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
37PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_RDY. Supported peripheral buses: SPI, ADC, PWM, RTC/CLK.
38PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
39PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
40PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
41PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
42PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_RDYMDF1CKI4. Supported peripheral buses: SPI.
43PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSMDF1SDI5. Supported peripheral buses: SPI.
44PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKMDF1CKI5. Supported peripheral buses: SPI.
45PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
46PE15Digital_IOSignal terminal PE15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI.
47PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL, SPI2_SCKUSART3TX. Supported peripheral buses: SPI, I2C.
48VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
49VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
51PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI, I2C.
52PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
53PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, SPI2_MISO. Supported peripheral buses: UART, SPI, I2C.
54PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
55PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: UART.
56PH11Digital_IOSignal terminal PH11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH11. Supported peripheral buses: General.
57PH12Digital_IOSignal terminal PH12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH12. Supported peripheral buses: PWM.
58PH13Digital_IOSignal terminal PH13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH13. Supported peripheral buses: General.
59VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
60VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
61PH14Digital_IOSignal terminal PH14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH14. Supported peripheral buses: General.
62PH15Digital_IOSignal terminal PH15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH15. Supported peripheral buses: General.
63PI0Digital_IOSignal terminal PI0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI0. Supported peripheral buses: General.
64PI1Digital_IOSignal terminal PI1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK_OCTOSPIMP2IO2. Supported peripheral buses: SPI.
ExplorePartsPackagesMFRsUpload