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CH9104L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH9104L

WCHID: C22439562LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH9104L (LQFP-48(7x7))1GND2LOWPWR3DSR3/ GPIO324GND5VCC6RTS0/ TNOW0/7CTS0/ GPIO048TXD19RXD110RTS1/ TNOW1/11CTS1/ GPIO1412DTR1/ GPIO1313DSR1/ GPIO1214DCD1/ GPIO1115RI1/ RWK1/ G16DTR0/GPIO0317DSR0/ GPIO0218VCC19GND20DCD0/ GPIO0121RI0/ RWK0/ G22TXD223RXD224RTS2/ TNOW2/48DTR3/ GPIO3347CTS3/ GPIO3446RTS3/ TNOW3/45VCC44NC43UD+42UD-41GND40GND39RXD338TXD337RI3/ RWK3/ G36CFG135CFG034DCD3/ GPIO3133VCC32GND31RXD030TXD029RI2/ RWK2/ G28DCD2/ GPIO2127DSR2/ GPIO2226DTR2/ GPIO2325CTS2/ GPIO24Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GNDGNDGround Reference Pin (GND)
2LOWPWRI/OMultiplexed I/O & Peripheral Pin LOWPWR (General)
3DSR3/ GPIO32I/OMultiplexed I/O & Peripheral Pin DSR3/ GPIO32 (UART)
4GNDGNDGround Reference Pin (GND)
5VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
6RTS0/ TNOW0/ GPIO05I/OMultiplexed I/O & Peripheral Pin RTS0/ TNOW0/ GPIO05 (UART)
7CTS0/ GPIO04I/OMultiplexed I/O & Peripheral Pin CTS0/ GPIO04 (UART)
8TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
9RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
10RTS1/ TNOW1/ GPIO15I/OMultiplexed I/O & Peripheral Pin RTS1/ TNOW1/ GPIO15 (UART)
11CTS1/ GPIO14I/OMultiplexed I/O & Peripheral Pin CTS1/ GPIO14 (UART)
12DTR1/ GPIO13I/OMultiplexed I/O & Peripheral Pin DTR1/ GPIO13 (UART)
13DSR1/ GPIO12I/OMultiplexed I/O & Peripheral Pin DSR1/ GPIO12 (UART)
14DCD1/ GPIO11I/OMultiplexed I/O & Peripheral Pin DCD1/ GPIO11 (General)
15RI1/ RWK1/ GPIO10I/OMultiplexed I/O & Peripheral Pin RI1/ RWK1/ GPIO10 (General)
16DTR0/GPIO03I/OMultiplexed I/O & Peripheral Pin DTR0/GPIO03 (UART)
17DSR0/ GPIO02I/OMultiplexed I/O & Peripheral Pin DSR0/ GPIO02 (UART)
18VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
19GNDGNDGround Reference Pin (GND)
20DCD0/ GPIO01I/OMultiplexed I/O & Peripheral Pin DCD0/ GPIO01 (UART)
21RI0/ RWK0/ GPIO00I/OMultiplexed I/O & Peripheral Pin RI0/ RWK0/ GPIO00 (USB, UART)
22TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
23RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
24RTS2/ TNOW2/ GPIO25I/OMultiplexed I/O & Peripheral Pin RTS2/ TNOW2/ GPIO25 (UART)
25CTS2/ GPIO24I/OMultiplexed I/O & Peripheral Pin CTS2/ GPIO24 (UART)
26DTR2/ GPIO23I/OMultiplexed I/O & Peripheral Pin DTR2/ GPIO23 (UART)
27DSR2/ GPIO22I/OMultiplexed I/O & Peripheral Pin DSR2/ GPIO22 (UART)
28DCD2/ GPIO21I/OMultiplexed I/O & Peripheral Pin DCD2/ GPIO21 (General)
29RI2/ RWK2/ GPIO20I/OMultiplexed I/O & Peripheral Pin RI2/ RWK2/ GPIO20 (General)
30TXD0I/OTXD0 (UART)
31RXD0I/ORXD0 (UART)
32GNDGNDGround Reference Pin (GND)
33VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
34DCD3/ GPIO31I/OMultiplexed I/O & Peripheral Pin DCD3/ GPIO31 (General)
35CFG0I/OMultiplexed I/O & Peripheral Pin CFG0 (General)
36CFG1I/OMultiplexed I/O & Peripheral Pin CFG1 (General)
37RI3/ RWK3/ GPIO30I/OMultiplexed I/O & Peripheral Pin RI3/ RWK3/ GPIO30 (General)
38TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
39RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
40GNDGNDGround Reference Pin (GND)
41GNDGNDGround Reference Pin (GND)
42UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
43UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
44NCI/OMultiplexed I/O & Peripheral Pin NC (General)
45VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
46RTS3/ TNOW3/ GPIO35I/OMultiplexed I/O & Peripheral Pin RTS3/ TNOW3/ GPIO35 (UART)
47CTS3/ GPIO34I/OMultiplexed I/O & Peripheral Pin CTS3/ GPIO34 (UART)
48DTR3/ GPIO33I/OMultiplexed I/O & Peripheral Pin DTR3/ GPIO33 (UART)
PIN 1 GND
GND
Ground Reference Pin (GND)
Design note: 公共接地端 需要连接USB总线的地线 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH9104L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH9104L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH9104L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH9104L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH9104L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH9104L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH9104L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH9104
P2 · p02_fig01EXACT PACKAGE
CH9104L (LQFP-48(7x7)) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP48 7*7mm 0.5mm 19.7mil 标准LQFP48 脚贴片 CH9104L
封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP48 7*7mm 0.5mm 19.7mil 标准LQFP48 脚贴片 CH9104L
P2 · p02_fig02EXACT PACKAGE
CH9104L (LQFP-48(7x7)) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP48 7*7mm 0.5mm 19.7mil 标准LQFP48 脚贴片 CH9104L | 注：CH9104 的USB 收发器按USB2.0 全内置设计，UD+和UD-引脚不能串接电阻，否则影响信号质量。 | 4、引脚 | 引脚号 引脚名称 类型 引脚说明 | 5、18、33、 45 VCC 电源 正电源输入端，需要外接退耦电容 | 1、4、19、 32、40、41 GND 电源 公共接地端，需要连接USB 总线的地线
封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP48 7*7mm 0.5mm 19.7mil 标准LQFP48 脚贴片 CH9104L | 注：CH9104 的USB 收发器按USB2.0 全内置设计，UD+和UD-引脚不能串接电阻，否则影响信号质量。 | 4、引脚 | 引脚号 引脚名称 类型 引脚说明 | 5、18、33、 45 VCC 电源 正电源输入端，需要外接退耦电容 | 1、4、19、 32、40、41 GND 电源 公共接地端，需要连接USB 总线的地线
P1 · p01_fig011387×530px
CH9104L (LQFP-48(7x7)) — CH9104 是一款USB 总线的转接芯片，实现USB 转四个异步串口UART0/1/2/3 功能，用于为计算 机扩展异步串口，或者将普通的串口设备或者MCU 直接升级到USB 总线。
CH9104 是一款USB 总线的转接芯片，实现USB 转四个异步串口UART0/1/2/3 功能，用于为计算 机扩展异步串口，或者将普通的串口设备或者MCU 直接升级到USB 总线。
P2 · p02_fig01P2
CH9104L (LQFP-48(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P6 · p06_fig011726×2138px
CH9104L (LQFP-48(7x7)) — 下图是由CH9104 芯片实现的USB 转四路TTL 串口的参考电路图。图中的信号线可以只连接RXDx、 TXDx 以及公共地线，其它信号线CTSx、RTSx/TNOWx、DTRx、DSRx、RIx 和DCDx 根据需要选用，不需 要时都可以悬空。
下图是由CH9104 芯片实现的USB 转四路TTL 串口的参考电路图。图中的信号线可以只连接RXDx、 TXDx 以及公共地线，其它信号线CTSx、RTSx/TNOWx、DTRx、DSRx、RIx 和DCDx 根据需要选用，不需 要时都可以悬空。
P6 · p06_fig01P6
CH9104L (LQFP-48(7x7)) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)
P7 · p07_fig011884×1479px
CH9104L (LQFP-48(7x7)) — 建议为USB 信号线增加ESD 保护器件，ESD 芯片寄生电容需小于2pF，例如CH412K。 建议串口外设与CH9104 芯片使用同一电源，否则需考虑分开供电时的IO 引脚倒灌电流问题。 在设计印刷线路板PCB 时，需要注意：退耦电容C5、C6、C7 和C8 尽量靠近CH9104 相连的电源 引脚；USB 口的D+和D-信号线按高速USB 规范贴近平行布线，保证特性阻抗，尽量在两侧提供地线 或者覆铜，减少来自外界的信号干扰。 | +3V3 | VIN 3 | GND 1 |
建议为USB 信号线增加ESD 保护器件，ESD 芯片寄生电容需小于2pF，例如CH412K。 建议串口外设与CH9104 芯片使用同一电源，否则需考虑分开供电时的IO 引脚倒灌电流问题。 在设计印刷线路板PCB 时，需要注意：退耦电容C5、C6、C7 和C8 尽量靠近CH9104 相连的电源 引脚；USB 口的D+和D-信号线按高速USB 规范贴近平行布线，保证特性阻抗，尽量在两侧提供地线 或者覆铜，减少来自外界的信号干扰。 | +3V3 | VIN 3 | GND 1 |

Technical Specifications & Part Details (CH9104L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH9104L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH9104L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH9104L (LQFP-48(7x7))?

Manufactured by WCH, the CH9104L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch. Key pins include: 1 (GND: Ground Reference Pin (GND)), 2 (LOWPWR: Multiplexed I/O & Peripheral Pin LOWPWR (General)), 3 (DSR3/ GPIO32: Multiplexed I/O & Peripheral Pin DSR3/ GPIO32 (UART)), 4 (GND: Ground Reference Pin (GND)), 5 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 6 (RTS0/ TNOW0/ GPIO05: Multiplexed I/O & Peripheral Pin RTS0/ TNOW0/ GPIO05 (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH9104L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH9104L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH9104L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH9104L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH9104 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
2LOWPWRDigital_IOSignal terminal LOWPWR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOWPWR. Supported peripheral buses: General.
3DSR3/ GPIO32Digital_IOSignal terminal DSR3/ GPIO32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR3/ GPIO32. Supported peripheral buses: UART.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6RTS0/ TNOW0/ GPIO05Digital_IOSignal terminal RTS0/ TNOW0/ GPIO05 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0/ TNOW0/ GPIO05. Supported peripheral buses: UART.
7CTS0/ GPIO04Digital_IOSignal terminal CTS0/ GPIO04 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0/ GPIO04. Supported peripheral buses: UART.
8TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
9RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
10RTS1/ TNOW1/ GPIO15Digital_IOSignal terminal RTS1/ TNOW1/ GPIO15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1/ TNOW1/ GPIO15. Supported peripheral buses: UART.
11CTS1/ GPIO14Digital_IOSignal terminal CTS1/ GPIO14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1/ GPIO14. Supported peripheral buses: UART.
12DTR1/ GPIO13Digital_IOSignal terminal DTR1/ GPIO13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1/ GPIO13. Supported peripheral buses: UART.
13DSR1/ GPIO12Digital_IOSignal terminal DSR1/ GPIO12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1/ GPIO12. Supported peripheral buses: UART.
14DCD1/ GPIO11Digital_IOSignal terminal DCD1/ GPIO11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1/ GPIO11. Supported peripheral buses: General.
15RI1/ RWK1/ GPIO10Digital_IOSignal terminal RI1/ RWK1/ GPIO10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1/ RWK1/ GPIO10. Supported peripheral buses: General.
16DTR0/GPIO03Digital_IOSignal terminal DTR0/GPIO03 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0/GPIO03. Supported peripheral buses: UART.
17DSR0/ GPIO02Digital_IOSignal terminal DSR0/ GPIO02 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0/ GPIO02. Supported peripheral buses: UART.
18VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
20DCD0/ GPIO01Digital_IOSignal terminal DCD0/ GPIO01 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0/ GPIO01. Supported peripheral buses: UART.
21RI0/ RWK0/ GPIO00Digital_IOSignal terminal RI0/ RWK0/ GPIO00 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0/ RWK0/ GPIO00. Supported peripheral buses: USB, UART.
22TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
23RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
24RTS2/ TNOW2/ GPIO25Digital_IOSignal terminal RTS2/ TNOW2/ GPIO25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS2/ TNOW2/ GPIO25. Supported peripheral buses: UART.
25CTS2/ GPIO24Digital_IOSignal terminal CTS2/ GPIO24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2/ GPIO24. Supported peripheral buses: UART.
26DTR2/ GPIO23Digital_IOSignal terminal DTR2/ GPIO23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR2/ GPIO23. Supported peripheral buses: UART.
27DSR2/ GPIO22Digital_IOSignal terminal DSR2/ GPIO22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR2/ GPIO22. Supported peripheral buses: UART.
28DCD2/ GPIO21Digital_IOSignal terminal DCD2/ GPIO21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD2/ GPIO21. Supported peripheral buses: General.
29RI2/ RWK2/ GPIO20Digital_IOSignal terminal RI2/ RWK2/ GPIO20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI2/ RWK2/ GPIO20. Supported peripheral buses: General.
30TXD0Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
31RXD0Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
32GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
33VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
34DCD3/ GPIO31Digital_IOSignal terminal DCD3/ GPIO31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD3/ GPIO31. Supported peripheral buses: General.
35CFG0Digital_IOSignal terminal CFG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG0. Supported peripheral buses: General.
36CFG1Digital_IOSignal terminal CFG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CFG1. Supported peripheral buses: General.
37RI3/ RWK3/ GPIO30Digital_IOSignal terminal RI3/ RWK3/ GPIO30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI3/ RWK3/ GPIO30. Supported peripheral buses: General.
38TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
39RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
40GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
41GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
42UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
43UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
44NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
45VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46RTS3/ TNOW3/ GPIO35Digital_IOSignal terminal RTS3/ TNOW3/ GPIO35 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS3/ TNOW3/ GPIO35. Supported peripheral buses: UART.
47CTS3/ GPIO34Digital_IOSignal terminal CTS3/ GPIO34 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3/ GPIO34. Supported peripheral buses: UART.
48DTR3/ GPIO33Digital_IOSignal terminal DTR3/ GPIO33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR3/ GPIO33. Supported peripheral buses: UART.
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