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STM32WBA55UGI6 (UFBGA-59(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32WBA55UGI6

STID: C22387508UFBGA-59(5x5) · 59 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32WBA55UGI6 (UFBGA-59(5x5))A1VSSSMPSA2PB14A3PA10A4VDDRFPAA5OSC_OUTA6VDDRFA7VSSRFA8RFB1VDDSMPSB2PB13B3PA9B4VDDHPAB5OSC_INB6VDDANAB7VSSRFB8NRSTC1VLXSMPSC2PB12C3VDD11C6VDDC7PH3_BOOT0C8PB15D1PA8D2PB11D4VSSD5VDDD6VSSD7PB0D8PB1E1PA6H8PB4H7PB5H6PB7H5PB8H4PC14_OSC32_IH3PB9H2PA1H1PA0G8PA15G7PB3G6PB6G5PC13G4PC15_OSC32_OG3PA2G2PA3G1PA4F8PA13F7PA12F6PA14F5VDDF3PA5F2VSSAF1VDDAE8PA11E7PB2E5VSSE4VDDE3VSSE2PA7Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.843.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1A2B2C2D2E2F2G2H2A3B3C3E3F3G3H3A4B4D4E4G4H4A5B5D5E5F5G5H5A6B6C6D6F6G6H6A7B7C7D7E7F7G7H7A8B8C8D8E8F8G8H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (59/59)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSSMPSGNDGround Reference Pin (VSSSMPS)
A2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
A3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
A4VDDRFPAPowerPower Supply Input (VDDRFPA — 3.3V VDD (Max 4.0V))
A5OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
A6VDDRFPowerPower Supply Input (VDDRF — 3.3V VDD (Max 4.0V))
A7VSSRFGNDGround Reference Pin (VSSRF)
A8RFI/OMultiplexed I/O & Peripheral Pin RF (General)
B1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
B2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
B3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
B4VDDHPAPowerPower Supply Input (VDDHPA — 3.3V VDD (Max 4.0V))
B5OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
B6VDDANAPowerPower Supply Input (VDDANA — 3.3V VDD (Max 4.0V))
B7VSSRFGNDGround Reference Pin (VSSRF)
B8NRSTISystem Enable & Hardware Reset (NRST)
C1VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
C2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
C3VDD11PowerPower Supply Input (VDD11 — 3.3V VDD (Max 4.0V))
C6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C7PH3_BOOT0I/OMultiplexed I/O & Peripheral Pin PH3_BOOT0 (General)
C8PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
D2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
D4VSSGNDGround Reference Pin (VSS)
D5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D6VSSGNDGround Reference Pin (VSS)
D7PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
D8PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
E1PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
E2PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
E3VSSGNDGround Reference Pin (VSS)
E4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E5VSSGNDGround Reference Pin (VSS)
E7PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
E8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
F1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
F2VSSAGNDGround Reference Pin (VSSA)
F3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
F7PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
F8PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
G1PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
G2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
G3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
G4PC15_OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15_OSC32_OUT (RTC/CLK)
G5PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
G6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
G7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
G8PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
H1PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
H3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
H4PC14_OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14_OSC32_IN (RTC/CLK)
H5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
H6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
H7PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
H8PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
PIN A1 VSSSMPS
GND
Ground Reference Pin (VSSSMPS)
Design note: 0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32WBA55UGI6 (ST · UFBGA-59(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32WBA55UGI6 (UFBGA-59(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32WBA55UGI6 (UFBGA-59(5x5)) - 2. Standard Pinout (Top View)
True package pinout (59 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32WBA55UGI6 (UFBGA-59(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32WBA55UGI6 (UFBGA-59(5x5)) - 4. Package Dimensions (D×E×A)
UFBGA-59(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32WBA55UGI6 (UFBGA-59(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (59 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32WBA55UGI6 (UFBGA-59(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32WBA55 / STM32WBA54
P148 · p148_fig01EXACT PACKAGE
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 43. UFBGA59 - Recommended footprint
Figure 43. UFBGA59 - Recommended footprint
P1 · p01_fig01881×726px
STM32WBA55UGI6 (UFBGA-59(5x5)) — • Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU running at up to 100 MHz
• Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU running at up to 100 MHz
P66 · p66_fig011546×916px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 7. UFQFPN32 pinout(1) (2)
Figure 7. UFQFPN32 pinout(1) (2)
P66 · p66_fig021546×906px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 8. WLCSP41 pinout(1) 4
Figure 8. WLCSP41 pinout(1) 4
P67 · p67_fig011546×1060px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 9. UFQFPN48 pinout(1) (2)
Figure 9. UFQFPN48 pinout(1) (2)
P67 · p67_fig021546×1039px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 10. UFQFPN48 SMPS pinout(1) (2)
Figure 10. UFQFPN48 SMPS pinout(1) (2)
P67 · p67_fig01P67
STM32WBA55UGI6 (UFBGA-59(5x5)) — Datasheet Page 67 (p67_fig01)
Datasheet Page 67 (p67_fig01)
P79 · p79_fig011546×1398px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 14. Power supply scheme with LDO
Figure 14. Power supply scheme with LDO
P79 · p79_fig01P79
STM32WBA55UGI6 (UFBGA-59(5x5)) — Datasheet Page 79 (p79_fig01)
Datasheet Page 79 (p79_fig01)
P80 · p80_fig011546×1879px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 15. Power supply scheme with SMPS
Figure 15. Power supply scheme with SMPS
P81 · p81_fig011546×1849px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 16. Power supply scheme with SMPS (high RF power)
Figure 16. Power supply scheme with SMPS (high RF power)
P140 · p140_fig011546×937px
STM32WBA55UGI6 (UFBGA-59(5x5)) — Figure 37. UFQFPN32 - Recommended footprint
Figure 37. UFQFPN32 - Recommended footprint
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32WBA55UGI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32WBA55UGI6 (UFBGA-59(5x5)) is a 59-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-59(5x5))
Pin Count & Lead PitchN / e
59 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, I2C, ADC, JTAG / SWD, IrDA, PWM, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3_BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol59 auto-grouped pins
OK
IPC-7351B Land Pattern59 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-59(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.23 × 0.23 mm
Pins / Total PadsTopology
59P / 59Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-59(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32WBA55UGI6 (UFBGA-59(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32WBA55UGI6 (UFBGA-59(5x5))?

Manufactured by ST, the STM32WBA55UGI6 is housed in a UFBGA-59(5x5) package with 59 pins and a 0.50 mm lead pitch. Key pins include: A1 (VSSSMPS: Ground Reference Pin (VSSSMPS)), A2 (PB14: Multiplexed I/O & Peripheral Pin PB14 (General)), A3 (PA10: Multiplexed I/O & Peripheral Pin PA10 (General)), A4 (VDDRFPA: Power Supply Input (VDDRFPA — 3.3V VDD (Max 4.0V))), A5 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)), A6 (VDDRF: Power Supply Input (VDDRF — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32WBA55UGI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32WBA55UGI6 (UFBGA-59(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 59 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32WBA55UGI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32WBA55UGI6 (ST, UFBGA-59(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (59 pins) & STM32WBA55 / STM32WBA54 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
A2PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
A3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
A4VDDRFPAPower_InPrimary positive power supply input (VDDRFPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A5OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
A6VDDRFPower_InPrimary positive power supply input (VDDRF) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A7VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
A8RFRF_50OhmSignal terminal RF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: RF. Supported peripheral buses: General.
B1VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
B3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
B4VDDHPAPower_InPrimary positive power supply input (VDDHPA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B5OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
B6VDDANAPower_InPrimary positive power supply input (VDDANA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B7VSSRFGND0V electrical ground return terminal (VSSRF) for internal core logic, I/O drivers, and analog sub-blocks.
B8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
C1VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
C2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
C3VDD11Power_InPrimary positive power supply input (VDD11) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C7PH3_BOOT0Digital_IOSignal terminal PH3_BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3_BOOT0. Supported peripheral buses: General.
C8PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
D2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
D4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D7PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
D8PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
E1PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
E2PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
E3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E7PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
E8PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
F1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F2VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
F5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F6PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
F7PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
F8PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
G1PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
G2PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
G3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
G4PC15_OSC32_OUTDigital_IOSignal terminal PC15_OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15_OSC32_OUT. Supported peripheral buses: RTC/CLK.
G5PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
G6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
G7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
G8PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
H1PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
H3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
H4PC14_OSC32_INDigital_IOSignal terminal PC14_OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14_OSC32_IN. Supported peripheral buses: RTC/CLK.
H5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
H6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
H7PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
H8PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
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