PIC16LF876A-I/SO (SOIC-28-300mil) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16LF876A-I/SO (SOIC-28-300mil)?

Manufactured by MICROCHIP, the PIC16LF876A-I/SO is housed in a SOIC-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR#/VPP: Multiplexed I/O & Peripheral Pin MCLR#/VPP (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16LF876A-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF876A-I/SO (SOIC-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF876A-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF876A-I/SO (MICROCHIP, SOIC-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.50mm × 17.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	MCLR#/VPP	I/O	Multiplexed I/O & Peripheral Pin MCLR#/VPP (General)
2	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
3	RA1/AN1	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1 (General)
4	RA2/AN2/VREF-/CVREF	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)
5	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
6	RA4/T0CKI/C1OUT	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)
7	RA5/AN4/SS#/C2OUT	I/O	Multiplexed I/O & Peripheral Pin RA5/AN4/SS#/C2OUT (General)
8	VSS	GND	Ground Reference Pin (VSS)
9	OSC1/CLKI	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKI (RTC/CLK)
10	OSC2/CLKO	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKO (RTC/CLK)
11	RC0/T1OSO/T1CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
12	RC1/T1OSI/CCP2	I/O	Multiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
13	RC2/CCP1	I/O	Multiplexed I/O & Peripheral Pin RC2/CCP1 (General)
14	RC3/SCK/SCL	I/O	Multiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
15	RC4/SDI/SDA	I/O	Multiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
16	RC5/SDO	I/O	Multiplexed I/O & Peripheral Pin RC5/SDO (General)
17	RC6/TX/CK	I/O	Multiplexed I/O & Peripheral Pin RC6/TX/CK (General)
18	RC7/RX/DT	I/O	Multiplexed I/O & Peripheral Pin RC7/RX/DT (General)
19	VSS	GND	Ground Reference Pin (VSS)
20	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
21	RB0/INT	I/O	Multiplexed I/O & Peripheral Pin RB0/INT (General)
22	RB1	I/O	Multiplexed I/O & Peripheral Pin RB1 (General)
23	RB2	I/O	Multiplexed I/O & Peripheral Pin RB2 (General)
24	RB3/PGM	I/O	Multiplexed I/O & Peripheral Pin RB3/PGM (General)
25	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
26	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
27	RB6/PGC	I/O	Multiplexed I/O & Peripheral Pin RB6/PGC (General)
28	RB7/PGD	I/O	Multiplexed I/O & Peripheral Pin RB7/PGD (General)

PIN 1 MCLR#/VPP

I/O

Multiplexed I/O & Peripheral Pin MCLR#/VPP (General)

Design note: Signal terminal MCLR#/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16LF876A-I/SO (SOIC-28-300mil) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16LF876A-I/SO (SOIC-28-300mil) - 2. Standard Pinout (Top View)

True package pinout (28 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16LF876A-I/SO (SOIC-28-300mil) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16LF876A-I/SO (SOIC-28-300mil) - 4. Package Dimensions (D×E×A)

SOIC-28-300mil · 7.50×17.90mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16LF876A-I/SO (SOIC-28-300mil) - 5. Recommended Land Pattern

IPC-7351B Footprint (28 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16LF876A-I/SO (SOIC-28-300mil) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for PIC16LF876A / PIC16F876AT

P2 · p02_fig021229×907px

44 43 42 41 40 39 16 17

P2 · p02_fig03938×950px

8 9

P65 · p65_fig011753×607px

FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM

P66 · p66_fig01867×721px

PIC16LF876A-I/SO (SOIC-28-300mil) — FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) and set bit GO/DONE (ADCON0<2>).

FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) and set bit GO/DONE (ADCON0<2>).

P75 · p75_fig011777×938px

FIGURE 9-2: SPI MASTER/SLAVE CONNECTION

P78 · p78_fig011777×1087px

FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 0) Write to SSPBUF

P78 · p78_fig021777×1126px

FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 1) Write to SSPBUF

P78 · p78_fig01P78

Datasheet Page 78 (p78_fig01)

P213 · p213_fig011441×1814px

PIC16LF876A-I/SO (SOIC-28-300mil) — CH2 x 45 CH1 x 45 | 10 5 0 10 5 0  Mold Draft Angle Bottom | 10 5 0 10 5 0  Mold Draft Angle Top | 0.53 0.51 0.33 .021 .020 .013 B | 0.81 0.74 0.66 .032 .029 .026 B1 Upper Lead Width | 0.33 0.27 0.20 .013 .011 .008 c Lead Thickness | 11

P216 · p216_fig011442×1787px

PIC16LF876A-I/SO (SOIC-28-300mil) — Foot Angle Top  0 4 8 0 4 8 | 15 12 0 15 12 0  Mold Draft Angle Bottom | 15 12 0 15 12 0  Mold Draft Angle Top | 0.51 0.42 0.36 .020 .017 .014 B Lead Width | 0.33 0.28 0.23 .013 .011 .009 c Lead Thickness | 1.27 0.84 0.41 .050 .033 .016

P216 · p216_fig01P216

Datasheet Page 216 (p216_fig01)

P2 · p02_fig01All Packages in PDF

28-Pin QFN

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC16LF876A-I/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16LF876A-I/SO (SOIC-28-300mil) is a 28-pin standard electronic & interconnect component featuring a 17.90 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

20 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

17.90 × 7.50 × 2.70 mm (A1=0.20 mm)

Package family: SOIC (SOIC-28-300mil)

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol28 auto-grouped pins

IPC-7351B Land Pattern28 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — PIC16LF876A / PIC16F876AT (2)

Select package variant or sibling MPN sharing this datasheet

SOIC-28-300mil · 28P

PIC16LF876A-I/SO

MICROCHIP·SOIC-28-300mil

IPC-7351B

28P17.9×7.5×2.70mmP=1.27mm

PIC16LF876A / PIC16F876AT (SOIC-28-300mil)

QFN-28-EP(6x6) · 29P

PIC16F876AT-E/ML

MICROCHIP·QFN-28-EP(6x6)

IPC-7351B

29P6.0×6.0×0.85mmP=0.65mm

PIC16LF876A / PIC16F876AT (QFN-28-EP(6x6))

Mechanical Dimensions & Land Pattern (SOIC-28-300mil)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

17.90 × 7.50 mm

Height (A) & Pitch (e)IPC-7351B

A=2.70mm · e=1.27mm

Pad Size (W × L)Level B

0.60 × 1.90 mm

Pins / Total PadsTopology

28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOIC-28-300mil	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF876A-I/SO (SOIC-28-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF876A-I/SO (SOIC-28-300mil)?

Manufactured by MICROCHIP, the PIC16LF876A-I/SO is housed in a SOIC-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR#/VPP: Multiplexed I/O & Peripheral Pin MCLR#/VPP (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF876A-I/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF876A-I/SO (SOIC-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF876A-I/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF876A-I/SO (MICROCHIP, SOIC-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & PIC16LF876A / PIC16F876AT Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	MCLR#/VPP	Digital_IO	Signal terminal MCLR#/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP. Supported peripheral buses: General.
2	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
3	RA1/AN1	Digital_IO	Signal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
4	RA2/AN2/VREF-/CVREF	Analog	Signal terminal RA2/AN2/VREF-/CVREF (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.
5	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
6	RA4/T0CKI/C1OUT	Digital_IO	Signal terminal RA4/T0CKI/C1OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT. Supported peripheral buses: General.
7	RA5/AN4/SS#/C2OUT	Digital_IO	Signal terminal RA5/AN4/SS#/C2OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/SS#/C2OUT. Supported peripheral buses: General.
8	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9	OSC1/CLKI	Digital_IO	Signal terminal OSC1/CLKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI. Supported peripheral buses: RTC/CLK.
10	OSC2/CLKO	Digital_IO	Signal terminal OSC2/CLKO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO. Supported peripheral buses: RTC/CLK.
11	RC0/T1OSO/T1CKI	Digital_IO	Signal terminal RC0/T1OSO/T1CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
12	RC1/T1OSI/CCP2	Digital_IO	Signal terminal RC1/T1OSI/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
13	RC2/CCP1	Digital_IO	Signal terminal RC2/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
14	RC3/SCK/SCL	Digital_IO	Signal terminal RC3/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
15	RC4/SDI/SDA	Digital_IO	Signal terminal RC4/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
16	RC5/SDO	Digital_IO	Signal terminal RC5/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
17	RC6/TX/CK	Digital_IO	Signal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
18	RC7/RX/DT	Digital_IO	Signal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
19	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
21	RB0/INT	Digital_IO	Signal terminal RB0/INT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
22	RB1	Digital_IO	Signal terminal RB1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
23	RB2	Digital_IO	Signal terminal RB2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
24	RB3/PGM	Digital_IO	Signal terminal RB3/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/PGM. Supported peripheral buses: General.
25	RB4	Digital_IO	Signal terminal RB4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
26	RB5	Digital_IO	Signal terminal RB5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
27	RB6/PGC	Digital_IO	Signal terminal RB6/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/PGC. Supported peripheral buses: General.
28	RB7/PGD	Digital_IO	Signal terminal RB7/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/PGD. Supported peripheral buses: General.

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