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PIC16F1947-I/MR (QFN-64-EP(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F1947-I/MR

MICROCHIPID: C220670QFN-64-EP(9x9) · 65 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F1947-I/MR (QFN-64-EP(9x9))1Y2Y3—4Y5Y6Y7—8Y9Vss10Vdd11Y12Y13Y14Y15Y16Y17Y18Y19—20—21SEG3522SEG3423SEG1824SEG3325Vss26Vdd27SEG1528SEG1429SEG3230SEG4031SEG2732SEG2833SEG1365EP64Y63—62—61—60—59—58SEG057Vdd56Vss55SEG154SEG253SEG352SEG451SEG550SEG649SEG748SEG3047SEG846SEG945SEG1044SEG1143SEG2942SEG3841Vss40SEG3639SEG3738Vdd37SEG3936SEG1235SEG1634SEG17Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=9.00mm · Pitch e=0.50mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1YI/OMultiplexed I/O & Peripheral Pin Y (General)
2YI/OMultiplexed I/O & Peripheral Pin Y (General)
3—I/OMultiplexed I/O & Peripheral Pin — (General)
4YI/OMultiplexed I/O & Peripheral Pin Y (General)
5YI/OMultiplexed I/O & Peripheral Pin Y (General)
6YI/OMultiplexed I/O & Peripheral Pin Y (General)
7—I/OMultiplexed I/O & Peripheral Pin — (General)
8YI/OMultiplexed I/O & Peripheral Pin Y (General)
9VssGNDGround Reference Pin (Vss)
10VddPowerPower Supply Input (Vdd — 1.8V-5.5V)
11YI/OMultiplexed I/O & Peripheral Pin Y (General)
12YI/OMultiplexed I/O & Peripheral Pin Y (General)
13YI/OMultiplexed I/O & Peripheral Pin Y (General)
14YI/OMultiplexed I/O & Peripheral Pin Y (General)
15YI/OMultiplexed I/O & Peripheral Pin Y (General)
16YI/OMultiplexed I/O & Peripheral Pin Y (General)
17YI/OMultiplexed I/O & Peripheral Pin Y (General)
18YI/OMultiplexed I/O & Peripheral Pin Y (General)
19—I/OMultiplexed I/O & Peripheral Pin — (General)
20—I/OMultiplexed I/O & Peripheral Pin — (General)
21SEG35I/OMultiplexed I/O & Peripheral Pin SEG35 (General)
22SEG34I/OMultiplexed I/O & Peripheral Pin SEG34 (General)
23SEG18I/OMultiplexed I/O & Peripheral Pin SEG18 (General)
24SEG33I/OMultiplexed I/O & Peripheral Pin SEG33 (General)
25VssGNDGround Reference Pin (Vss)
26VddPowerPower Supply Input (Vdd — 1.8V-5.5V)
27SEG15I/OMultiplexed I/O & Peripheral Pin SEG15 (General)
28SEG14I/OMultiplexed I/O & Peripheral Pin SEG14 (General)
29SEG32I/OMultiplexed I/O & Peripheral Pin SEG32 (General)
30SEG40I/OMultiplexed I/O & Peripheral Pin SEG40 (General)
31SEG27I/OMultiplexed I/O & Peripheral Pin SEG27 (General)
32SEG28I/OMultiplexed I/O & Peripheral Pin SEG28 (General)
33SEG13I/OMultiplexed I/O & Peripheral Pin SEG13 (General)
34SEG17I/OMultiplexed I/O & Peripheral Pin SEG17 (General)
35SEG16I/OMultiplexed I/O & Peripheral Pin SEG16 (General)
36SEG12I/OMultiplexed I/O & Peripheral Pin SEG12 (General)
37SEG39I/OMultiplexed I/O & Peripheral Pin SEG39 (General)
38VddPowerPower Supply Input (Vdd — 1.8V-5.5V)
39SEG37I/OMultiplexed I/O & Peripheral Pin SEG37 (General)
40SEG36I/OMultiplexed I/O & Peripheral Pin SEG36 (General)
41VssGNDGround Reference Pin (Vss)
42SEG38I/OMultiplexed I/O & Peripheral Pin SEG38 (General)
43SEG29I/OMultiplexed I/O & Peripheral Pin SEG29 (General)
44SEG11I/OMultiplexed I/O & Peripheral Pin SEG11 (General)
45SEG10I/OMultiplexed I/O & Peripheral Pin SEG10 (General)
46SEG9I/OMultiplexed I/O & Peripheral Pin SEG9 (General)
47SEG8I/OMultiplexed I/O & Peripheral Pin SEG8 (General)
48SEG30I/OMultiplexed I/O & Peripheral Pin SEG30 (General)
49SEG7I/OMultiplexed I/O & Peripheral Pin SEG7 (General)
50SEG6I/OMultiplexed I/O & Peripheral Pin SEG6 (General)
51SEG5I/OMultiplexed I/O & Peripheral Pin SEG5 (General)
52SEG4I/OMultiplexed I/O & Peripheral Pin SEG4 (General)
53SEG3I/OMultiplexed I/O & Peripheral Pin SEG3 (General)
54SEG2I/OMultiplexed I/O & Peripheral Pin SEG2 (General)
55SEG1I/OMultiplexed I/O & Peripheral Pin SEG1 (General)
56VssGNDGround Reference Pin (Vss)
57VddPowerPower Supply Input (Vdd — 1.8V-5.5V)
58SEG0I/OMultiplexed I/O & Peripheral Pin SEG0 (General)
59—I/OMultiplexed I/O & Peripheral Pin — (General)
60—I/OMultiplexed I/O & Peripheral Pin — (General)
61—I/OMultiplexed I/O & Peripheral Pin — (General)
62—I/OMultiplexed I/O & Peripheral Pin — (General)
63—I/OMultiplexed I/O & Peripheral Pin — (General)
64YI/OMultiplexed I/O & Peripheral Pin Y (General)
65EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 Y
I/O
Multiplexed I/O & Peripheral Pin Y (General)
Design note: Signal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F1947-I/MR (MICROCHIP · QFN-64-EP(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 4. Package Dimensions (D×E×A)
QFN-64-EP(9x9) · 9.00×9.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F1947-I/MR (QFN-64-EP(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for PIC16F1947
P1 · p01_fig01377×200px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and XLP Technology
64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and XLP Technology
P205 · p205_fig011753×665px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 23-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 23-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P207 · p207_fig011763×824px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 23-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 23-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P207 · p207_fig021784×612px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — PIC16(L)F1946/47 ECCP1, ECCP2, CCP3, CCP4, CCP5
PIC16(L)F1946/47 ECCP1, ECCP2, CCP3, CCP4, CCP5
P214 · p214_fig011536×1053px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 23-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
FIGURE 23-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
P214 · p214_fig01P214
PIC16F1947-I/MR (QFN-64-EP(9x9)) — Datasheet Page 214 (p214_fig01)
Datasheet Page 214 (p214_fig01)
P225 · p225_fig011698×565px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 23-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)
FIGURE 23-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0)
P225 · p225_fig021777×721px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 23-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1)
FIGURE 23-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1)
P361 · p361_fig011416×1013px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
P361 · p361_fig01P361
PIC16F1947-I/MR (QFN-64-EP(9x9)) — Datasheet Page 361 (p361_fig01)
Datasheet Page 361 (p361_fig01)
P447 · p447_fig011713×1865px
PIC16F1947-I/MR (QFN-64-EP(9x9)) — 33.1 Package Marking Information
33.1 Package Marking Information
P447 · p447_fig01P447
PIC16F1947-I/MR (QFN-64-EP(9x9)) — Datasheet Page 447 (p447_fig01)
Datasheet Page 447 (p447_fig01)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (PIC16F1947-I/MR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F1947-I/MR (QFN-64-EP(9x9)) is a 64-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V-5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, DAC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V-5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-64-EP(9x9))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.45×5.45mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-64-EP(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-64-EP(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F1947-I/MR (QFN-64-EP(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F1947-I/MR (QFN-64-EP(9x9))?

Manufactured by MICROCHIP, the PIC16F1947-I/MR is housed in a QFN-64-EP(9x9) package with 65 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V-5.5V. Key pins include: 1 (Y: Multiplexed I/O & Peripheral Pin Y (General)), 2 (Y: Multiplexed I/O & Peripheral Pin Y (General)), 3 (—: Multiplexed I/O & Peripheral Pin — (General)), 4 (Y: Multiplexed I/O & Peripheral Pin Y (General)), 5 (Y: Multiplexed I/O & Peripheral Pin Y (General)), 6 (Y: Multiplexed I/O & Peripheral Pin Y (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F1947-I/MR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F1947-I/MR (QFN-64-EP(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.50 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 5.45 × 5.45 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F1947-I/MR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F1947-I/MR (MICROCHIP, QFN-64-EP(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & PIC16F1947 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
2YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
3—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
4YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
5YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
6YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
7—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
8YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
9VssGND0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
10VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V-5.5V domain (Max rating: 5.5V).
11YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
12YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
13YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
14YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
15YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
16YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
17YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
18YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
19—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
20—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
21SEG35Digital_IOSignal terminal SEG35 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG35. Supported peripheral buses: General.
22SEG34Digital_IOSignal terminal SEG34 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG34. Supported peripheral buses: General.
23SEG18Digital_IOSignal terminal SEG18 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG18. Supported peripheral buses: General.
24SEG33Digital_IOSignal terminal SEG33 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG33. Supported peripheral buses: General.
25VssGND0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
26VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V-5.5V domain (Max rating: 5.5V).
27SEG15Digital_IOSignal terminal SEG15 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG15. Supported peripheral buses: General.
28SEG14Digital_IOSignal terminal SEG14 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG14. Supported peripheral buses: General.
29SEG32Digital_IOSignal terminal SEG32 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG32. Supported peripheral buses: General.
30SEG40Digital_IOSignal terminal SEG40 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG40. Supported peripheral buses: General.
31SEG27Digital_IOSignal terminal SEG27 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG27. Supported peripheral buses: General.
32SEG28Digital_IOSignal terminal SEG28 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG28. Supported peripheral buses: General.
33SEG13Digital_IOSignal terminal SEG13 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG13. Supported peripheral buses: General.
34SEG17Digital_IOSignal terminal SEG17 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG17. Supported peripheral buses: General.
35SEG16Digital_IOSignal terminal SEG16 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG16. Supported peripheral buses: General.
36SEG12Digital_IOSignal terminal SEG12 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG12. Supported peripheral buses: General.
37SEG39Digital_IOSignal terminal SEG39 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG39. Supported peripheral buses: General.
38VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V-5.5V domain (Max rating: 5.5V).
39SEG37Digital_IOSignal terminal SEG37 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG37. Supported peripheral buses: General.
40SEG36Digital_IOSignal terminal SEG36 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG36. Supported peripheral buses: General.
41VssGND0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
42SEG38Digital_IOSignal terminal SEG38 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG38. Supported peripheral buses: General.
43SEG29Digital_IOSignal terminal SEG29 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG29. Supported peripheral buses: General.
44SEG11Digital_IOSignal terminal SEG11 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG11. Supported peripheral buses: General.
45SEG10Digital_IOSignal terminal SEG10 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG10. Supported peripheral buses: General.
46SEG9Digital_IOSignal terminal SEG9 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG9. Supported peripheral buses: General.
47SEG8Digital_IOSignal terminal SEG8 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG8. Supported peripheral buses: General.
48SEG30Digital_IOSignal terminal SEG30 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG30. Supported peripheral buses: General.
49SEG7Digital_IOSignal terminal SEG7 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
50SEG6Digital_IOSignal terminal SEG6 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG6. Supported peripheral buses: General.
51SEG5Digital_IOSignal terminal SEG5 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG5. Supported peripheral buses: General.
52SEG4Digital_IOSignal terminal SEG4 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG4. Supported peripheral buses: General.
53SEG3Digital_IOSignal terminal SEG3 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG3. Supported peripheral buses: General.
54SEG2Digital_IOSignal terminal SEG2 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG2. Supported peripheral buses: General.
55SEG1Digital_IOSignal terminal SEG1 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG1. Supported peripheral buses: General.
56VssGND0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
57VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V-5.5V domain (Max rating: 5.5V).
58SEG0Digital_IOSignal terminal SEG0 (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: SEG0. Supported peripheral buses: General.
59—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
60—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
61—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
62—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
63—Digital_IOSignal terminal — (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
64YDigital_IOSignal terminal Y (I/O, 1.8V-5.5V domain). Multiplexed alternate functions: Y. Supported peripheral buses: General.
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