HV5622PG-G (PQFP-44(10x10)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of HV5622PG-G (PQFP-44(10x10))?

Manufactured by MICROCHIP, the HV5622PG-G is housed in a PQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (HVOUT17: Multiplexed I/O & Peripheral Pin HVOUT17 (General)), 2 (HVOUT16: Multiplexed I/O & Peripheral Pin HVOUT16 (General)), 3 (HVOUT15: Multiplexed I/O & Peripheral Pin HVOUT15 (General)), 4 (HVOUT14: Multiplexed I/O & Peripheral Pin HVOUT14 (General)), 5 (HVOUT13: Multiplexed I/O & Peripheral Pin HVOUT13 (General)), 6 (HVOUT12: Multiplexed I/O & Peripheral Pin HVOUT12 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for HV5622PG-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV5622PG-G (PQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV5622PG-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV5622PG-G (MICROCHIP, PQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	HVOUT17	I/O	Multiplexed I/O & Peripheral Pin HVOUT17 (General)
2	HVOUT16	I/O	Multiplexed I/O & Peripheral Pin HVOUT16 (General)
3	HVOUT15	I/O	Multiplexed I/O & Peripheral Pin HVOUT15 (General)
4	HVOUT14	I/O	Multiplexed I/O & Peripheral Pin HVOUT14 (General)
5	HVOUT13	I/O	Multiplexed I/O & Peripheral Pin HVOUT13 (General)
6	HVOUT12	I/O	Multiplexed I/O & Peripheral Pin HVOUT12 (General)
7	HVOUT11	I/O	Multiplexed I/O & Peripheral Pin HVOUT11 (General)
8	HVOUT10	I/O	Multiplexed I/O & Peripheral Pin HVOUT10 (General)
9	HVOUT9	I/O	Multiplexed I/O & Peripheral Pin HVOUT9 (General)
10	HVOUT8	I/O	Multiplexed I/O & Peripheral Pin HVOUT8 (General)
11	HVOUT7	I/O	Multiplexed I/O & Peripheral Pin HVOUT7 (General)
12	HVOUT6	I/O	Multiplexed I/O & Peripheral Pin HVOUT6 (General)
13	HVOUT5	I/O	Multiplexed I/O & Peripheral Pin HVOUT5 (General)
14	HVOUT4	I/O	Multiplexed I/O & Peripheral Pin HVOUT4 (General)
15	HVOUT3	I/O	Multiplexed I/O & Peripheral Pin HVOUT3 (General)
16	HVOUT2	I/O	Multiplexed I/O & Peripheral Pin HVOUT2 (General)
17	HVOUT1	I/O	Multiplexed I/O & Peripheral Pin HVOUT1 (General)
18	DATAOUT	I/O	Multiplexed I/O & Peripheral Pin DATAOUT (General)
19	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
20	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
21	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
22	POL	I/O	Multiplexed I/O & Peripheral Pin POL (General)
23	CLK	I/O	Multiplexed I/O & Peripheral Pin CLK (General)
24	VSS	GND	Ground Reference Pin (VSS)
25	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
26	LE	I/O	Multiplexed I/O & Peripheral Pin LE (General)
27	POL	I/O	Multiplexed I/O & Peripheral Pin POL (General)
28	CLK	I/O	Multiplexed I/O & Peripheral Pin CLK (General)
29	VSS	GND	Ground Reference Pin (VSS)
30	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
31	LE	I/O	Multiplexed I/O & Peripheral Pin LE (General)
32	DATAIN	Analog	Multiplexed I/O & Peripheral Pin DATAIN (General)
33	BL	I/O	Multiplexed I/O & Peripheral Pin BL (General)
34	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
35	HVOUT32	I/O	Multiplexed I/O & Peripheral Pin HVOUT32 (General)
36	HVOUT31	I/O	Multiplexed I/O & Peripheral Pin HVOUT31 (General)
37	HVOUT30	I/O	Multiplexed I/O & Peripheral Pin HVOUT30 (General)
38	HVOUT29	I/O	Multiplexed I/O & Peripheral Pin HVOUT29 (General)
39	HVOUT28	I/O	Multiplexed I/O & Peripheral Pin HVOUT28 (General)
40	HVOUT27	I/O	Multiplexed I/O & Peripheral Pin HVOUT27 (General)
41	HVOUT26	I/O	Multiplexed I/O & Peripheral Pin HVOUT26 (General)
42	HVOUT25	I/O	Multiplexed I/O & Peripheral Pin HVOUT25 (General)
43	HVOUT24	I/O	Multiplexed I/O & Peripheral Pin HVOUT24 (General)
44	HVOUT23	I/O	Multiplexed I/O & Peripheral Pin HVOUT23 (General)

PIN 1 HVOUT17

I/O

Multiplexed I/O & Peripheral Pin HVOUT17 (General)

Design note: High -voltage output

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

HV5622PG-G (PQFP-44(10x10)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

HV5622PG-G (PQFP-44(10x10)) - 2. Standard Pinout (Top View)

True package pinout (44 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

HV5622PG-G (PQFP-44(10x10)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

HV5622PG-G (PQFP-44(10x10)) - 4. Package Dimensions (D×E×A)

PQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›

5. Recommended Land PatternLAND PATTERN

HV5622PG-G (PQFP-44(10x10)) - 5. Recommended Land Pattern

IPC-7351B Footprint (44 Pads)Expand ›

6. Application SchematicSCHEMATIC

HV5622PG-G (PQFP-44(10x10)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for HV5622

P1 · p01_fig01376×200px

32-Channel Serial-to-Parallel Converter With Open Drain Outputs

P1 · p01_fig02875×785px

 2017 Microchip Technology Inc. DS20005854A-page 1

P1 · p01_fig03466×615px

See Table 2-1 and Table 2-2 for pin information.

P2 · p02_fig011385×834px

Functional Block Diagram

P3 · p03_fig011408×875px

Typical Application Circuit

P3 · p03_fig01P3

Datasheet Page 3 (p03_fig01)

P11 · p11_fig011777×2204px

HV5622PG-G (PQFP-44(10x10)) —  2017 Microchip Technology Inc. DS20005854A-page 11 | 3 e | 3 e | 44-lead PQFP Example | XXXXXXXXX | YYWWNNN e3 | HV5622PG | 1724198 e3 | 44-lead PLCC Example | XXXXXXXXXXX | YYWWNNN e3 | HV5622PJ | 1722741 e3

P12 · p12_fig011777×1873px

HV5622PG-G (PQFP-44(10x10)) — 44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch | Symbol A A1 A2 b D D1 E E1 e L L1 L2 ș | Dimension | (mm) | MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 BSC | 0.73 1.95 REF | 0.25 BSC | 0

44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch | Symbol A A1 A2 b D D1 E E1 e L L1 L2 ș | Dimension | (mm) | MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 BSC | 0.73 1.95 REF | 0.25 BSC | 0

P12 · p12_fig01P12

Datasheet Page 12 (p12_fig01)

P13 · p13_fig011777×1878px

HV5622PG-G (PQFP-44(10x10)) — 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch | Symbol A A1 A2 b b1 D D1 E E1 e R | Dimension | (inches) | MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 | .050 BSC | .025 | NOM .172 .105 - - - .690

44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch | Symbol A A1 A2 b b1 D D1 E E1 e R | Dimension | (inches) | MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 | .050 BSC | .025 | NOM .172 .105 - - - .690

Technical Specifications & Part Details (HV5622PG-G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:HV5622PG-G (PQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 2.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 40°C to +85°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

8 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

10.00 × 10.00 × 2.20 mm (A1=0.10 mm)

Package family: TQFP (PQFP-44(10x10))

Pin Count & Lead PitchN / e

44 Pins | Pitch e = 0.80 mm (31.5 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol44 auto-grouped pins

IPC-7351B Land Pattern44 pads · Pitch 0.80mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 10.00 mm

Height (A) & Pitch (e)IPC-7351B

A=2.20mm · e=0.80mm

Pad Size (W × L)Level B

0.42 × 2.50 mm

Pins / Total PadsTopology

44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PQFP-44(10x10)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — HV5622PG-G (PQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of HV5622PG-G (PQFP-44(10x10))?

Manufactured by MICROCHIP, the HV5622PG-G is housed in a PQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (HVOUT17: Multiplexed I/O & Peripheral Pin HVOUT17 (General)), 2 (HVOUT16: Multiplexed I/O & Peripheral Pin HVOUT16 (General)), 3 (HVOUT15: Multiplexed I/O & Peripheral Pin HVOUT15 (General)), 4 (HVOUT14: Multiplexed I/O & Peripheral Pin HVOUT14 (General)), 5 (HVOUT13: Multiplexed I/O & Peripheral Pin HVOUT13 (General)), 6 (HVOUT12: Multiplexed I/O & Peripheral Pin HVOUT12 (General)).

What are the IPC-7351B PCB Footprint dimensions for HV5622PG-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), HV5622PG-G (PQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for HV5622PG-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for HV5622PG-G (MICROCHIP, PQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & HV5622 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	HVOUT17	Digital_IO	Signal terminal HVOUT17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT17. Supported peripheral buses: General.
2	HVOUT16	Digital_IO	Signal terminal HVOUT16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT16. Supported peripheral buses: General.
3	HVOUT15	Digital_IO	Signal terminal HVOUT15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT15. Supported peripheral buses: General.
4	HVOUT14	Digital_IO	Signal terminal HVOUT14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT14. Supported peripheral buses: General.
5	HVOUT13	Digital_IO	Signal terminal HVOUT13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT13. Supported peripheral buses: General.
6	HVOUT12	Digital_IO	Signal terminal HVOUT12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT12. Supported peripheral buses: General.
7	HVOUT11	Digital_IO	Signal terminal HVOUT11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT11. Supported peripheral buses: General.
8	HVOUT10	Digital_IO	Signal terminal HVOUT10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT10. Supported peripheral buses: General.
9	HVOUT9	Digital_IO	Signal terminal HVOUT9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT9. Supported peripheral buses: General.
10	HVOUT8	Digital_IO	Signal terminal HVOUT8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT8. Supported peripheral buses: General.
11	HVOUT7	Digital_IO	Signal terminal HVOUT7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT7. Supported peripheral buses: General.
12	HVOUT6	Digital_IO	Signal terminal HVOUT6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT6. Supported peripheral buses: General.
13	HVOUT5	Digital_IO	Signal terminal HVOUT5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT5. Supported peripheral buses: General.
14	HVOUT4	Digital_IO	Signal terminal HVOUT4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT4. Supported peripheral buses: General.
15	HVOUT3	Digital_IO	Signal terminal HVOUT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT3. Supported peripheral buses: General.
16	HVOUT2	Digital_IO	Signal terminal HVOUT2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT2. Supported peripheral buses: General.
17	HVOUT1	Digital_IO	Signal terminal HVOUT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT1. Supported peripheral buses: General.
18	DATAOUT	Digital_IO	Signal terminal DATAOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAOUT. Supported peripheral buses: General.
19	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
21	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22	POL	Digital_IO	Signal terminal POL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: POL. Supported peripheral buses: General.
23	CLK	Digital_IO	Signal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
24	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26	LE	Digital_IO	Signal terminal LE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LE. Supported peripheral buses: General.
27	POL	Digital_IO	Signal terminal POL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: POL. Supported peripheral buses: General.
28	CLK	Digital_IO	Signal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
29	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
30	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
31	LE	Digital_IO	Signal terminal LE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LE. Supported peripheral buses: General.
32	DATAIN	Analog	Signal terminal DATAIN (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATAIN. Supported peripheral buses: General.
33	BL	Digital_IO	Signal terminal BL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BL. Supported peripheral buses: General.
34	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35	HVOUT32	Digital_IO	Signal terminal HVOUT32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT32. Supported peripheral buses: General.
36	HVOUT31	Digital_IO	Signal terminal HVOUT31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT31. Supported peripheral buses: General.
37	HVOUT30	Digital_IO	Signal terminal HVOUT30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT30. Supported peripheral buses: General.
38	HVOUT29	Digital_IO	Signal terminal HVOUT29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT29. Supported peripheral buses: General.
39	HVOUT28	Digital_IO	Signal terminal HVOUT28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT28. Supported peripheral buses: General.
40	HVOUT27	Digital_IO	Signal terminal HVOUT27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT27. Supported peripheral buses: General.
41	HVOUT26	Digital_IO	Signal terminal HVOUT26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT26. Supported peripheral buses: General.
42	HVOUT25	Digital_IO	Signal terminal HVOUT25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT25. Supported peripheral buses: General.
43	HVOUT24	Digital_IO	Signal terminal HVOUT24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT24. Supported peripheral buses: General.
44	HVOUT23	Digital_IO	Signal terminal HVOUT23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HVOUT23. Supported peripheral buses: General.

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