USB2241-AEZG-06 (QFN-36-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of USB2241-AEZG-06 (QFN-36-EP(6x6))?

Manufactured by MICROCHIP, the USB2241-AEZG-06 is housed in a QFN-36-EP(6x6) package with 37 pins and a 0.50 mm lead pitch. Key pins include: 1 (LED: Multiplexed I/O & Peripheral Pin LED (CAN)), 2 (USB+: Multiplexed I/O & Peripheral Pin USB+ (USB)), 3 (USB-: Multiplexed I/O & Peripheral Pin USB- (USB)), 4 (SD_D1/MS_D5: Multiplexed I/O & Peripheral Pin SD_D1/MS_D5 (General)), 5 (SD_D0/MS_D4: Multiplexed I/O & Peripheral Pin SD_D0/MS_D4 (General)), 6 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)).

Q: What are the IPC-7351B PCB Footprint dimensions for USB2241-AEZG-06?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), USB2241-AEZG-06 (QFN-36-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 3.95 × 3.95 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for USB2241-AEZG-06?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for USB2241-AEZG-06 (MICROCHIP, QFN-36-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	LED	I/O	Multiplexed I/O & Peripheral Pin LED (CAN)
2	USB+	I/O	Multiplexed I/O & Peripheral Pin USB+ (USB)
3	USB-	I/O	Multiplexed I/O & Peripheral Pin USB- (USB)
4	SD_D1/MS_D5	I/O	Multiplexed I/O & Peripheral Pin SD_D1/MS_D5 (General)
5	SD_D0/MS_D4	I/O	Multiplexed I/O & Peripheral Pin SD_D0/MS_D4 (General)
6	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
7	SD_D7/MS_D6	I/O	Multiplexed I/O & Peripheral Pin SD_D7/MS_D6 (General)
8	SD_D6/MS_D7	I/O	Multiplexed I/O & Peripheral Pin SD_D6/MS_D7 (General)
9	SD_CLK	I/O	Multiplexed I/O & Peripheral Pin SD_CLK (General)
10	xD_ALE	I/O	Multiplexed I/O & Peripheral Pin xD_ALE (General)
11	SD_CMD	I/O	Multiplexed I/O & Peripheral Pin SD_CMD (General)
12	xD_nWE	I/O	Multiplexed I/O & Peripheral Pin xD_nWE (General)
13	VDD18	Power	Power Supply Input (VDD18 — 3.3V / 5.0V Standard Logic)
14	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
15	xD_nCE	I/O	Multiplexed I/O & Peripheral Pin xD_nCE (General)
16	xD_nRE	I/O	Multiplexed I/O & Peripheral Pin xD_nRE (General)
17	xD nB/R_	I/O	Multiplexed I/O & Peripheral Pin xD nB/R_ (General)
18	RESET_N	I	System Enable & Hardware Reset (RESET_N)
19	xD_nCD	I/O	Multiplexed I/O & Peripheral Pin xD_nCD (CAN)
20	SD_D4/MS_D2	I/O	Multiplexed I/O & Peripheral Pin SD_D4/MS_D2 (General)
21	CRD_PWR	I/O	Multiplexed I/O & Peripheral Pin CRD_PWR (General)
22	VDD33	Power	Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)
23	USB+ USB -	I/O	Multiplexed I/O & Peripheral Pin USB+ USB - (USB)
24	MS_INS	I/O	Multiplexed I/O & Peripheral Pin MS_INS (CAN)
25	SD_D2	I/O	Multiplexed I/O & Peripheral Pin SD_D2 (General)
26	SD_nCD	I/O	Multiplexed I/O & Peripheral Pin SD_nCD (General)
27	RXD/SDA	I/O	Multiplexed I/O & Peripheral Pin RXD/SDA (UART, I2C)
28	TEST	I/O	Multiplexed I/O & Peripheral Pin TEST (General)
29	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
30	MS_SCLK	I/O	Multiplexed I/O & Peripheral Pin MS_SCLK (SPI, I2C)
31	TXD / SCK / MS_SKTSEL_	I/O	Multiplexed I/O & Peripheral Pin TXD / SCK / MS_SKTSEL_ (UART, SPI)
32	XTAL2	I/O	Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
33	XTAL1 (CLKIN)	I/O	Multiplexed I/O & Peripheral Pin XTAL1 (CLKIN) (CAN, RTC/CLK)
34	VDD18PLL	Power	Power Supply Input (VDD18PLL — 3.3V / 5.0V Standard Logic)
35	RBIAS	I/O	Multiplexed I/O & Peripheral Pin RBIAS (USB)
36	VDDA33	Power	Power Supply Input (VDDA33 — 3.3V / 5.0V Standard Logic)
37	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 LED

I/O

Multiplexed I/O & Peripheral Pin LED (CAN)

Design note: LED: Can be used as an LED output .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (37 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-36-EP(6x6) · 6.00×6.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (37 Pads)Expand ›

6. Application SchematicSCHEMATIC

USB2241-AEZG-06 (QFN-36-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)

Showing 1–5 of 5 uncropped original figures for USB2241

P7 · p07_fig01EXACT PACKAGE

FIGURE 4-1: USB2240/USB2240I 36-PIN QFN DIAGRAM

P1 · p01_fig01377×200px

Ultra Fast USB 2.0 Multi-Format, SD/MMC, and MS Flash

P7 · p07_fig01P7

Datasheet Page 7 (p07_fig01)

P37 · p37_fig011777×2323px

11.0 PACKAGE OUTLINE

P37 · p37_fig02323×870px

 2010 - 2015 Microchip Technology Inc. DS00001979A-page 37

Technical Specifications & Part Details (USB2241-AEZG-06)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:USB2241-AEZG-06 (QFN-36-EP(6x6)) is a 36-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated Bluetooth / BLE, USB, CAN, I2C, RTC/CLK, SPI, UART interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

0°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

24 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (QFN-36-EP(6x6))

Pin Count & Lead PitchN / e

36 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Bluetooth / BLE, USB, CAN, I2C, RTC/CLK, SPI, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol37 auto-grouped pins

IPC-7351B Land Pattern37 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 3.95×3.95mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-36-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

37P / 37Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-36-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — USB2241-AEZG-06 (QFN-36-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of USB2241-AEZG-06 (QFN-36-EP(6x6))?

Manufactured by MICROCHIP, the USB2241-AEZG-06 is housed in a QFN-36-EP(6x6) package with 37 pins and a 0.50 mm lead pitch. Key pins include: 1 (LED: Multiplexed I/O & Peripheral Pin LED (CAN)), 2 (USB+: Multiplexed I/O & Peripheral Pin USB+ (USB)), 3 (USB-: Multiplexed I/O & Peripheral Pin USB- (USB)), 4 (SD_D1/MS_D5: Multiplexed I/O & Peripheral Pin SD_D1/MS_D5 (General)), 5 (SD_D0/MS_D4: Multiplexed I/O & Peripheral Pin SD_D0/MS_D4 (General)), 6 (VDD33: Power Supply Input (VDD33 — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for USB2241-AEZG-06?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), USB2241-AEZG-06 (QFN-36-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 3.95 × 3.95 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for USB2241-AEZG-06?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for USB2241-AEZG-06 (MICROCHIP, QFN-36-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & USB2241 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	LED	Digital_IO	Signal terminal LED (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LED. Supported peripheral buses: CAN.
2	USB+	Digital_IO	Signal terminal USB+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB+. Supported peripheral buses: USB.
3	USB-	Digital_IO	Signal terminal USB- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB-. Supported peripheral buses: USB.
4	SD_D1/MS_D5	Digital_IO	Signal terminal SD_D1/MS_D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D1/MS_D5. Supported peripheral buses: General.
5	SD_D0/MS_D4	Digital_IO	Signal terminal SD_D0/MS_D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D0/MS_D4. Supported peripheral buses: General.
6	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7	SD_D7/MS_D6	Digital_IO	Signal terminal SD_D7/MS_D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D7/MS_D6. Supported peripheral buses: General.
8	SD_D6/MS_D7	Digital_IO	Signal terminal SD_D6/MS_D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D6/MS_D7. Supported peripheral buses: General.
9	SD_CLK	Digital_IO	Signal terminal SD_CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CLK. Supported peripheral buses: General.
10	xD_ALE	Digital_IO	Signal terminal xD_ALE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD_ALE. Supported peripheral buses: General.
11	SD_CMD	Digital_IO	Signal terminal SD_CMD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_CMD. Supported peripheral buses: General.
12	xD_nWE	Digital_IO	Signal terminal xD_nWE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD_nWE. Supported peripheral buses: General.
13	VDD18	Power_In	Primary positive power supply input (VDD18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15	xD_nCE	Digital_IO	Signal terminal xD_nCE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD_nCE. Supported peripheral buses: General.
16	xD_nRE	Digital_IO	Signal terminal xD_nRE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD_nRE. Supported peripheral buses: General.
17	xD nB/R_	Digital_IO	Signal terminal xD nB/R_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD nB/R_. Supported peripheral buses: General.
18	RESET_N	Digital_IO	Active-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
19	xD_nCD	Digital_IO	Signal terminal xD_nCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: xD_nCD. Supported peripheral buses: CAN.
20	SD_D4/MS_D2	Digital_IO	Signal terminal SD_D4/MS_D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D4/MS_D2. Supported peripheral buses: General.
21	CRD_PWR	Digital_IO	Signal terminal CRD_PWR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CRD_PWR. Supported peripheral buses: General.
22	VDD33	Power_In	Primary positive power supply input (VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
23	USB+ USB -	Digital_IO	Signal terminal USB+ USB - (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: USB+ USB -. Supported peripheral buses: USB.
24	MS_INS	Digital_IO	Signal terminal MS_INS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MS_INS. Supported peripheral buses: CAN.
25	SD_D2	Digital_IO	Signal terminal SD_D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_D2. Supported peripheral buses: General.
26	SD_nCD	Digital_IO	Signal terminal SD_nCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SD_nCD. Supported peripheral buses: General.
27	RXD/SDA	Digital_IO	Signal terminal RXD/SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD/SDA. Supported peripheral buses: UART, I2C.
28	TEST	Digital_IO	Signal terminal TEST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TEST. Supported peripheral buses: General.
29	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
30	MS_SCLK	Digital_IO	Signal terminal MS_SCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MS_SCLK. Supported peripheral buses: SPI, I2C.
31	TXD / SCK / MS_SKTSEL_	Digital_IO	Signal terminal TXD / SCK / MS_SKTSEL_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD / SCK / MS_SKTSEL_. Supported peripheral buses: UART, SPI.
32	XTAL2	Digital_IO	Signal terminal XTAL2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
33	XTAL1 (CLKIN)	Digital_IO	Signal terminal XTAL1 (CLKIN) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XTAL1 (CLKIN). Supported peripheral buses: CAN, RTC/CLK.
34	VDD18PLL	Power_In	Primary positive power supply input (VDD18PLL) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
35	RBIAS	Digital_IO	Signal terminal RBIAS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RBIAS. Supported peripheral buses: USB.
36	VDDA33	Power_In	Primary positive power supply input (VDDA33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
37	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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