ChipDocs.org
3921 PARTSUpload PDF
ATMEGA48-20PU (PDIP-28) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATMEGA48-20PU

MICROCHIPPDIP-28 · 28 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATMEGA48-20PU (PDIP-28)1(PCINT14/#RE2(PCINT16/RXD3(PCINT17/TXD4(PCINT18/INT5(PCINT19/OC26(PCINT20/XCK7VCC8GND9IO410IO511(PCINT21/OC012(PCINT22/OC013(PCINT23/AIN14(PCINT0/CLKO28PC5(ADC5/SCL27PC4(ADC4/SDA26PC3(ADC3/PCI25PC2(ADC2/PCI24PC1(ADC1/PCI23PC0(ADC0/PCI22GND21AREF20AVCC19PB5(SCK/PCIN18PB4(MISO/PCI17PB3(MOSI/OC216PB2(#SS/OC1B15PB1(OC1A/PCIGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=7.00mm · Pitch e=2.54mmD=7.00mm-14-12-10-8-6-4-20246810121427252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1(PCINT14/#RESET)PC6ISystem Enable & Hardware Reset ((PCINT14/#RESET)PC6)
2(PCINT16/RXD)PD0I/OMultiplexed I/O & Peripheral Pin (PCINT16/RXD)PD0 (UART)
3(PCINT17/TXD)PD1I/OMultiplexed I/O & Peripheral Pin (PCINT17/TXD)PD1 (UART)
4(PCINT18/INT0)PD2I/OMultiplexed I/O & Peripheral Pin (PCINT18/INT0)PD2 (General)
5(PCINT19/OC2B/INT1)PD3I/OMultiplexed I/O & Peripheral Pin (PCINT19/OC2B/INT1)PD3 (PWM)
6(PCINT20/XCK/T0)PD4I/OMultiplexed I/O & Peripheral Pin (PCINT20/XCK/T0)PD4 (General)
7VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
8GNDGNDGround Reference Pin (GND)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10IO5I/OGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11(PCINT21/OC0B/T1)PD5I/OMultiplexed I/O & Peripheral Pin (PCINT21/OC0B/T1)PD5 (PWM)
12(PCINT22/OC0A/AIN0)PD6I/OMultiplexed I/O & Peripheral Pin (PCINT22/OC0A/AIN0)PD6 (ADC, PWM)
13(PCINT23/AIN1)PD7I/OMultiplexed I/O & Peripheral Pin (PCINT23/AIN1)PD7 (ADC)
14(PCINT0/CLKO/ICP1)PB0I/OMultiplexed I/O & Peripheral Pin (PCINT0/CLKO/ICP1)PB0 (General)
15PB1(OC1A/PCINT1)I/OMultiplexed I/O & Peripheral Pin PB1(OC1A/PCINT1) (PWM)
16PB2(#SS/OC1B/PCINT2)I/OMultiplexed I/O & Peripheral Pin PB2(#SS/OC1B/PCINT2) (PWM)
17PB3(MOSI/OC2A/PCINT3)I/OMultiplexed I/O & Peripheral Pin PB3(MOSI/OC2A/PCINT3) (SPI, PWM)
18PB4(MISO/PCINT4)I/OMultiplexed I/O & Peripheral Pin PB4(MISO/PCINT4) (SPI)
19PB5(SCK/PCINT5)I/OMultiplexed I/O & Peripheral Pin PB5(SCK/PCINT5) (SPI)
20AVCCPowerPower Supply Input (AVCC — 1.8V ~ 5.5V VCC)
21AREFI/OMultiplexed I/O & Peripheral Pin AREF (ADC)
22GNDGNDGround Reference Pin (GND)
23PC0(ADC0/PCINT8)I/OMultiplexed I/O & Peripheral Pin PC0(ADC0/PCINT8) (ADC)
24PC1(ADC1/PCINT9)I/OMultiplexed I/O & Peripheral Pin PC1(ADC1/PCINT9) (ADC)
25PC2(ADC2/PCINT10)I/OMultiplexed I/O & Peripheral Pin PC2(ADC2/PCINT10) (ADC)
26PC3(ADC3/PCINT11)I/OMultiplexed I/O & Peripheral Pin PC3(ADC3/PCINT11) (ADC)
27PC4(ADC4/SDA/PCINT12)I/OMultiplexed I/O & Peripheral Pin PC4(ADC4/SDA/PCINT12) (I2C, ADC)
28PC5(ADC5/SCL/PCINT13)I/OMultiplexed I/O & Peripheral Pin PC5(ADC5/SCL/PCINT13) (I2C, ADC)
PIN 1 (PCINT14/#RESET)PC6
I
System Enable & Hardware Reset ((PCINT14/#RESET)PC6)
Design note: Active-low hardware reset terminal ((PCINT14/#RESET)PC6): pulling this pin Low resets the processor core and peripherals.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
ATMEGA48-20PU (PDIP-28) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATMEGA48-20PU (PDIP-28) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATMEGA48-20PU (PDIP-28) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATMEGA48-20PU (PDIP-28) - 4. Package Dimensions (D×E×A)
PDIP-28 · 7.00×7.00mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATMEGA48-20PU (PDIP-28) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATMEGA48-20PU (PDIP-28) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for ATMEGA48
P18 · p18_fig01EXACT PACKAGE
ATMEGA48-20PU (PDIP-28) — 6.2 28P3
6.2 28P3
P1 · p01_fig01652×576px
ATMEGA48-20PU (PDIP-28) — 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
P2 · p02_fig011956×1675px
ATMEGA48-20PU (PDIP-28) — Figure 1-1. Pinout ATmega48/88/168
Figure 1-1. Pinout ATmega48/88/168
P2 · p02_fig01P2
ATMEGA48-20PU (PDIP-28) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P18 · p18_fig01P18
ATMEGA48-20PU (PDIP-28) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P17 · p17_fig01All Packages in PDF
ATMEGA48-20PU (PDIP-28) — 17 | 2545ES-AVR-02/05 | ATmega48/88/168 | 6. Packaging Information | 6.1 32A | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile
17 | 2545ES-AVR-02/05 | ATmega48/88/168 | 6. Packaging Information | 6.1 32A | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile
P19 · p19_fig01All Packages in PDF
ATMEGA48-20PU (PDIP-28) — 19 | 2545ES-AVR-02/05 | ATmega48/88/168 | 6.3 32M1-A | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, D 32M1-A | 8/19/04 | 3.10 mm Exposed Pad, Micro Lead Fram
19 | 2545ES-AVR-02/05 | ATmega48/88/168 | 6.3 32M1-A | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, D 32M1-A | 8/19/04 | 3.10 mm Exposed Pad, Micro Lead Fram

Technical Specifications & Part Details (ATMEGA48-20PU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:ATMEGA48-20PU (PDIP-28) is a 28-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 3.85 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
28 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 3.85 mm (A1=0.51 mm)
Package family: DIP (PDIP-28)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-28)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.85mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
28P / 28Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-28
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATMEGA48-20PU (PDIP-28)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATMEGA48-20PU (PDIP-28)?

Manufactured by MICROCHIP, the ATMEGA48-20PU is housed in a PDIP-28 package with 28 pins and a 2.54 mm lead pitch. Key pins include: 1 ((PCINT14/#RESET)PC6: System Enable & Hardware Reset ((PCINT14/#RESET)PC6)), 2 ((PCINT16/RXD)PD0: Multiplexed I/O & Peripheral Pin (PCINT16/RXD)PD0 (UART)), 3 ((PCINT17/TXD)PD1: Multiplexed I/O & Peripheral Pin (PCINT17/TXD)PD1 (UART)), 4 ((PCINT18/INT0)PD2: Multiplexed I/O & Peripheral Pin (PCINT18/INT0)PD2 (General)), 5 ((PCINT19/OC2B/INT1)PD3: Multiplexed I/O & Peripheral Pin (PCINT19/OC2B/INT1)PD3 (PWM)), 6 ((PCINT20/XCK/T0)PD4: Multiplexed I/O & Peripheral Pin (PCINT20/XCK/T0)PD4 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATMEGA48-20PU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA48-20PU (PDIP-28) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 2.54 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA48-20PU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA48-20PU (MICROCHIP, PDIP-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & ATMEGA48 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1(PCINT14/#RESET)PC6Digital_IOActive-low hardware reset terminal ((PCINT14/#RESET)PC6): pulling this pin Low resets the processor core and peripherals.
2(PCINT16/RXD)PD0Digital_IOSignal terminal (PCINT16/RXD)PD0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT16/RXD)PD0. Supported peripheral buses: UART.
3(PCINT17/TXD)PD1Digital_IOSignal terminal (PCINT17/TXD)PD1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT17/TXD)PD1. Supported peripheral buses: UART.
4(PCINT18/INT0)PD2Digital_IOSignal terminal (PCINT18/INT0)PD2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT18/INT0)PD2. Supported peripheral buses: General.
5(PCINT19/OC2B/INT1)PD3Digital_IOSignal terminal (PCINT19/OC2B/INT1)PD3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT19/OC2B/INT1)PD3. Supported peripheral buses: PWM.
6(PCINT20/XCK/T0)PD4Digital_IOSignal terminal (PCINT20/XCK/T0)PD4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT20/XCK/T0)PD4. Supported peripheral buses: General.
7VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10IO5Digital_IOGPIO5 / RTC_GPIO5 / TOUCH5 / ADC1_CH4
11(PCINT21/OC0B/T1)PD5Digital_IOSignal terminal (PCINT21/OC0B/T1)PD5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT21/OC0B/T1)PD5. Supported peripheral buses: PWM.
12(PCINT22/OC0A/AIN0)PD6AnalogSignal terminal (PCINT22/OC0A/AIN0)PD6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT22/OC0A/AIN0)PD6. Supported peripheral buses: ADC, PWM.
13(PCINT23/AIN1)PD7AnalogSignal terminal (PCINT23/AIN1)PD7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT23/AIN1)PD7. Supported peripheral buses: ADC.
14(PCINT0/CLKO/ICP1)PB0Digital_IOSignal terminal (PCINT0/CLKO/ICP1)PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (PCINT0/CLKO/ICP1)PB0. Supported peripheral buses: General.
15PB1(OC1A/PCINT1)Digital_IOSignal terminal PB1(OC1A/PCINT1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB1(OC1A/PCINT1). Supported peripheral buses: PWM.
16PB2(#SS/OC1B/PCINT2)Digital_IOSignal terminal PB2(#SS/OC1B/PCINT2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB2(#SS/OC1B/PCINT2). Supported peripheral buses: PWM.
17PB3(MOSI/OC2A/PCINT3)Digital_IOSignal terminal PB3(MOSI/OC2A/PCINT3) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB3(MOSI/OC2A/PCINT3). Supported peripheral buses: SPI, PWM.
18PB4(MISO/PCINT4)Digital_IOSignal terminal PB4(MISO/PCINT4) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB4(MISO/PCINT4). Supported peripheral buses: SPI.
19PB5(SCK/PCINT5)Digital_IOSignal terminal PB5(SCK/PCINT5) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB5(SCK/PCINT5). Supported peripheral buses: SPI.
20AVCCPower_InPrimary positive power supply input (AVCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
21AREFDigital_IOSignal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AREF. Supported peripheral buses: ADC.
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23PC0(ADC0/PCINT8)AnalogSignal terminal PC0(ADC0/PCINT8) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC0(ADC0/PCINT8). Supported peripheral buses: ADC.
24PC1(ADC1/PCINT9)AnalogSignal terminal PC1(ADC1/PCINT9) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC1(ADC1/PCINT9). Supported peripheral buses: ADC.
25PC2(ADC2/PCINT10)AnalogSignal terminal PC2(ADC2/PCINT10) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC2(ADC2/PCINT10). Supported peripheral buses: ADC.
26PC3(ADC3/PCINT11)AnalogSignal terminal PC3(ADC3/PCINT11) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC3(ADC3/PCINT11). Supported peripheral buses: ADC.
27PC4(ADC4/SDA/PCINT12)Digital_IOSignal terminal PC4(ADC4/SDA/PCINT12) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC4(ADC4/SDA/PCINT12). Supported peripheral buses: I2C, ADC.
28PC5(ADC5/SCL/PCINT13)Digital_IOSignal terminal PC5(ADC5/SCL/PCINT13) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC5(ADC5/SCL/PCINT13). Supported peripheral buses: I2C, ADC.
ExplorePartsPackagesMFRsUpload