ATXMEGA128B1-AU (TQFP-100(14x14)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of ATXMEGA128B1-AU (TQFP-100(14x14))?

Manufactured by MICROCHIP, the ATXMEGA128B1-AU is housed in a TQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 2 (PC0: Multiplexed I/O & Peripheral Pin PC0 (General)), 3 (PC1: Multiplexed I/O & Peripheral Pin PC1 (General)), 4 (PC2: Multiplexed I/O & Peripheral Pin PC2 (General)), 5 (PC3: Multiplexed I/O & Peripheral Pin PC3 (General)), 6 (PC4: Multiplexed I/O & Peripheral Pin PC4 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for ATXMEGA128B1-AU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATXMEGA128B1-AU (TQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATXMEGA128B1-AU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATXMEGA128B1-AU (MICROCHIP, TQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
2	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (General)
3	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (General)
4	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (General)
5	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (General)
6	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (General)
7	PC5	I/O	Multiplexed I/O & Peripheral Pin PC5 (General)
8	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (General)
9	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (General)
10	GND	GND	Ground Reference Pin (GND)
11	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
12	PD0	I/O	Multiplexed I/O & Peripheral Pin PD0 (General)
13	PD1	I/O	Multiplexed I/O & Peripheral Pin PD1 (General)
14	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (General)
15	RESET	I	System Enable & Hardware Reset (RESET)
16	PDI	I/O	Multiplexed I/O & Peripheral Pin PDI (General)
17	GND	GND	Ground Reference Pin (GND)
18	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
19	PE0	I/O	Multiplexed I/O & Peripheral Pin PE0 (General)
20	PE1	I/O	Multiplexed I/O & Peripheral Pin PE1 (General)
21	PE2	I/O	Multiplexed I/O & Peripheral Pin PE2 (General)
22	PE3	I/O	Multiplexed I/O & Peripheral Pin PE3 (General)
23	PE4	I/O	Multiplexed I/O & Peripheral Pin PE4 (General)
24	PE5	I/O	Multiplexed I/O & Peripheral Pin PE5 (General)
25	PE6	I/O	Multiplexed I/O & Peripheral Pin PE6 (General)
26	PE7	I/O	Multiplexed I/O & Peripheral Pin PE7 (General)
27	GND	GND	Ground Reference Pin (GND)
28	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
29	SEG39	I/O	Multiplexed I/O & Peripheral Pin SEG39 (General)
30	SEG38	I/O	Multiplexed I/O & Peripheral Pin SEG38 (General)
31	SEG37	I/O	Multiplexed I/O & Peripheral Pin SEG37 (General)
32	SEG36	I/O	Multiplexed I/O & Peripheral Pin SEG36 (General)
33	SEG35	I/O	Multiplexed I/O & Peripheral Pin SEG35 (General)
34	SEG34	I/O	Multiplexed I/O & Peripheral Pin SEG34 (General)
35	SEG33	I/O	Multiplexed I/O & Peripheral Pin SEG33 (General)
36	SEG32	I/O	Multiplexed I/O & Peripheral Pin SEG32 (General)
37	SEG31	I/O	Multiplexed I/O & Peripheral Pin SEG31 (General)
38	SEG30	I/O	Multiplexed I/O & Peripheral Pin SEG30 (General)
39	SEG29	I/O	Multiplexed I/O & Peripheral Pin SEG29 (General)
40	SEG28	I/O	Multiplexed I/O & Peripheral Pin SEG28 (General)
41	SEG27	I/O	Multiplexed I/O & Peripheral Pin SEG27 (General)
42	SEG26	I/O	Multiplexed I/O & Peripheral Pin SEG26 (General)
43	SEG25	I/O	Multiplexed I/O & Peripheral Pin SEG25 (General)
44	SEG24	I/O	Multiplexed I/O & Peripheral Pin SEG24 (General)
45	SEG23	I/O	Multiplexed I/O & Peripheral Pin SEG23 (General)
46	SEG22	I/O	Multiplexed I/O & Peripheral Pin SEG22 (General)
47	SEG21	I/O	Multiplexed I/O & Peripheral Pin SEG21 (General)
48	SEG20	I/O	Multiplexed I/O & Peripheral Pin SEG20 (General)
49	SEG19	I/O	Multiplexed I/O & Peripheral Pin SEG19 (General)
50	SEG18	I/O	Multiplexed I/O & Peripheral Pin SEG18 (General)
51	SEG17	I/O	Multiplexed I/O & Peripheral Pin SEG17 (General)
52	SEG16	I/O	Multiplexed I/O & Peripheral Pin SEG16 (General)
53	SEG15	I/O	Multiplexed I/O & Peripheral Pin SEG15 (General)
54	SEG14	I/O	Multiplexed I/O & Peripheral Pin SEG14 (General)
55	SEG13	I/O	Multiplexed I/O & Peripheral Pin SEG13 (General)
56	SEG12	I/O	Multiplexed I/O & Peripheral Pin SEG12 (General)
57	SEG11	I/O	Multiplexed I/O & Peripheral Pin SEG11 (General)
58	SEG10	I/O	Multiplexed I/O & Peripheral Pin SEG10 (General)
59	SEG9	I/O	Multiplexed I/O & Peripheral Pin SEG9 (General)
60	SEG8	I/O	Multiplexed I/O & Peripheral Pin SEG8 (General)
61	SEG7	I/O	Multiplexed I/O & Peripheral Pin SEG7 (General)
62	SEG6	I/O	Multiplexed I/O & Peripheral Pin SEG6 (General)
63	SEG5	I/O	Multiplexed I/O & Peripheral Pin SEG5 (General)
64	SEG4	I/O	Multiplexed I/O & Peripheral Pin SEG4 (General)
65	SEG3	I/O	Multiplexed I/O & Peripheral Pin SEG3 (General)
66	SEG2	I/O	Multiplexed I/O & Peripheral Pin SEG2 (General)
67	SEG1	I/O	Multiplexed I/O & Peripheral Pin SEG1 (General)
68	SEG0	I/O	Multiplexed I/O & Peripheral Pin SEG0 (General)
69	GND	GND	Ground Reference Pin (GND)
70	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
71	BIAS1	I/O	Multiplexed I/O & Peripheral Pin BIAS1 (General)
72	BIAS2	I/O	Multiplexed I/O & Peripheral Pin BIAS2 (General)
73	VLCD	I/O	Multiplexed I/O & Peripheral Pin VLCD (General)
74	CAPL	I/O	Multiplexed I/O & Peripheral Pin CAPL (General)
75	CAPH	I/O	Multiplexed I/O & Peripheral Pin CAPH (General)
76	COM0	I/O	Multiplexed I/O & Peripheral Pin COM0 (General)
77	COM1	I/O	Multiplexed I/O & Peripheral Pin COM1 (General)
78	COM2	I/O	Multiplexed I/O & Peripheral Pin COM2 (General)
79	COM3	I/O	Multiplexed I/O & Peripheral Pin COM3 (General)
80	PR0	I/O	Multiplexed I/O & Peripheral Pin PR0 (General)
81	PR1	I/O	Multiplexed I/O & Peripheral Pin PR1 (General)
82	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (General)
83	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (General)
84	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (General)
85	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (General)
86	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (General)
87	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (General)
88	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (General)
89	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (General)
90	AGND	GND	Ground Reference Pin (AGND)
91	AVCC	Power	Power Supply Input (AVCC — 3.3V / 5.0V Standard Logic)
92	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (General)
93	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (General)
94	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (General)
95	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (General)
96	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (General)
97	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (General)
98	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (General)
99	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (General)
100	GND	GND	Ground Reference Pin (GND)

PIN 1 VCC

Power

Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)

Design note: Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ATXMEGA128B1-AU (TQFP-100(14x14)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ATXMEGA128B1-AU (TQFP-100(14x14)) - 2. Standard Pinout (Top View)

True package pinout (100 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ATXMEGA128B1-AU (TQFP-100(14x14)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ATXMEGA128B1-AU (TQFP-100(14x14)) - 4. Package Dimensions (D×E×A)

TQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

ATXMEGA128B1-AU (TQFP-100(14x14)) - 5. Recommended Land Pattern

IPC-7351B Footprint (100 Pads)Expand ›

6. Application SchematicSCHEMATIC

ATXMEGA128B1-AU (TQFP-100(14x14)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for ATXMEGA128B1

P67 · p67_fig01EXACT PACKAGE

67 XMEGA B1 [DATASHEET]

P4 · p04_fig012004×2193px

Figure 2-1. Block Diagram and Pinout

P21 · p21_fig011671×1808px

Figure 10-1. The Clock System, Clock Sources, and Clock Distribution

P21 · p21_fig01P21

Datasheet Page 21 (p21_fig01)

P48 · p48_fig011028×612px

Figure 28-1. LCD Overview

P54 · p54_fig012040×436px

The tables below show the notation for all pin functions available and describe its function.

P54 · p54_fig022040×437px

32.1.4 LCD Functions

P54 · p54_fig032040×642px

AREF Analog Reference input pin

P56 · p56_fig011909×363px

32.2 Alternate Pin Functions

P56 · p56_fig01P56

Datasheet Page 56 (p56_fig01)

P67 · p67_fig01P67

Datasheet Page 67 (p67_fig01)

P139 · p139_fig011742×1853px

ATXMEGA128B1-AU (TQFP-100(14x14)) — 39.5 8330D - 01/2013 | 39.6 8330C - 07/2012 | 39.7 8330B - 02/2012 | 39.8 8330A - 10/2011 | 1. Updated “Ordering Information” on page 2: Added -AUR, -CU and -CUR options. | 2. Updated “Packaging Information” : Added package drawing for “7A1

39.5 8330D - 01/2013 | 39.6 8330C - 07/2012 | 39.7 8330B - 02/2012 | 39.8 8330A - 10/2011 | 1. Updated “Ordering Information” on page 2: Added -AUR, -CU and -CUR options. | 2. Updated “Packaging Information” : Added package drawing for “7A1

Technical Specifications & Part Details (ATXMEGA128B1-AU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:ATXMEGA128B1-AU (TQFP-100(14x14)) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

12MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

14.00 × 14.00 × 1.20 mm (A1=0.10 mm)

Package family: TQFP (TQFP-100(14x14))

Pin Count & Lead PitchN / e

100 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, ADC, JTAG / SWD, IrDA

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol100 auto-grouped pins

IPC-7351B Land Pattern100 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

14.00 × 14.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.25 mm

Pins / Total PadsTopology

100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TQFP-100(14x14)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATXMEGA128B1-AU (TQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATXMEGA128B1-AU (TQFP-100(14x14))?

Manufactured by MICROCHIP, the ATXMEGA128B1-AU is housed in a TQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 2 (PC0: Multiplexed I/O & Peripheral Pin PC0 (General)), 3 (PC1: Multiplexed I/O & Peripheral Pin PC1 (General)), 4 (PC2: Multiplexed I/O & Peripheral Pin PC2 (General)), 5 (PC3: Multiplexed I/O & Peripheral Pin PC3 (General)), 6 (PC4: Multiplexed I/O & Peripheral Pin PC4 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATXMEGA128B1-AU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATXMEGA128B1-AU (TQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATXMEGA128B1-AU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATXMEGA128B1-AU (MICROCHIP, TQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & ATXMEGA128B1 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
3	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
4	PC2	Digital_IO	Signal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
5	PC3	Digital_IO	Signal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
6	PC4	Digital_IO	Signal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
7	PC5	Digital_IO	Signal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
8	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
9	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
10	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12	PD0	Digital_IO	Signal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
13	PD1	Digital_IO	Signal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
14	PD2	Digital_IO	Signal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
15	RESET	Digital_IO	Active-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
16	PDI	Digital_IO	Signal terminal PDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PDI. Supported peripheral buses: General.
17	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19	PE0	Digital_IO	Signal terminal PE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
20	PE1	Digital_IO	Signal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
21	PE2	Digital_IO	Signal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
22	PE3	Digital_IO	Signal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
23	PE4	Digital_IO	Signal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
24	PE5	Digital_IO	Signal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
25	PE6	Digital_IO	Signal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
26	PE7	Digital_IO	Signal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
27	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
28	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29	SEG39	Digital_IO	Signal terminal SEG39 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG39. Supported peripheral buses: General.
30	SEG38	Digital_IO	Signal terminal SEG38 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG38. Supported peripheral buses: General.
31	SEG37	Digital_IO	Signal terminal SEG37 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG37. Supported peripheral buses: General.
32	SEG36	Digital_IO	Signal terminal SEG36 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG36. Supported peripheral buses: General.
33	SEG35	Digital_IO	Signal terminal SEG35 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG35. Supported peripheral buses: General.
34	SEG34	Digital_IO	Signal terminal SEG34 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG34. Supported peripheral buses: General.
35	SEG33	Digital_IO	Signal terminal SEG33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG33. Supported peripheral buses: General.
36	SEG32	Digital_IO	Signal terminal SEG32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG32. Supported peripheral buses: General.
37	SEG31	Digital_IO	Signal terminal SEG31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG31. Supported peripheral buses: General.
38	SEG30	Digital_IO	Signal terminal SEG30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG30. Supported peripheral buses: General.
39	SEG29	Digital_IO	Signal terminal SEG29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG29. Supported peripheral buses: General.
40	SEG28	Digital_IO	Signal terminal SEG28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG28. Supported peripheral buses: General.
41	SEG27	Digital_IO	Signal terminal SEG27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG27. Supported peripheral buses: General.
42	SEG26	Digital_IO	Signal terminal SEG26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG26. Supported peripheral buses: General.
43	SEG25	Digital_IO	Signal terminal SEG25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG25. Supported peripheral buses: General.
44	SEG24	Digital_IO	Signal terminal SEG24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG24. Supported peripheral buses: General.
45	SEG23	Digital_IO	Signal terminal SEG23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG23. Supported peripheral buses: General.
46	SEG22	Digital_IO	Signal terminal SEG22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG22. Supported peripheral buses: General.
47	SEG21	Digital_IO	Signal terminal SEG21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG21. Supported peripheral buses: General.
48	SEG20	Digital_IO	Signal terminal SEG20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG20. Supported peripheral buses: General.
49	SEG19	Digital_IO	Signal terminal SEG19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG19. Supported peripheral buses: General.
50	SEG18	Digital_IO	Signal terminal SEG18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG18. Supported peripheral buses: General.
51	SEG17	Digital_IO	Signal terminal SEG17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG17. Supported peripheral buses: General.
52	SEG16	Digital_IO	Signal terminal SEG16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG16. Supported peripheral buses: General.
53	SEG15	Digital_IO	Signal terminal SEG15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG15. Supported peripheral buses: General.
54	SEG14	Digital_IO	Signal terminal SEG14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG14. Supported peripheral buses: General.
55	SEG13	Digital_IO	Signal terminal SEG13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG13. Supported peripheral buses: General.
56	SEG12	Digital_IO	Signal terminal SEG12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG12. Supported peripheral buses: General.
57	SEG11	Digital_IO	Signal terminal SEG11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG11. Supported peripheral buses: General.
58	SEG10	Digital_IO	Signal terminal SEG10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG10. Supported peripheral buses: General.
59	SEG9	Digital_IO	Signal terminal SEG9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG9. Supported peripheral buses: General.
60	SEG8	Digital_IO	Signal terminal SEG8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG8. Supported peripheral buses: General.
61	SEG7	Digital_IO	Signal terminal SEG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
62	SEG6	Digital_IO	Signal terminal SEG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG6. Supported peripheral buses: General.
63	SEG5	Digital_IO	Signal terminal SEG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG5. Supported peripheral buses: General.
64	SEG4	Digital_IO	Signal terminal SEG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG4. Supported peripheral buses: General.

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