PIC16F877-04/P (PDIP-40) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16F877-04/P (PDIP-40)?

Manufactured by MICROCHIP, the PIC16F877-04/P is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR/VPP: Multiplexed I/O & Peripheral Pin MCLR/VPP (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16F877-04/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F877-04/P (PDIP-40) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 2.54 mm, and 40 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F877-04/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F877-04/P (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 10.00mm × 10.00mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	MCLR/VPP	I/O	Multiplexed I/O & Peripheral Pin MCLR/VPP (General)
2	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
3	RA1/AN1	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1 (General)
4	RA2/AN2/VREF	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)
5	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
6	RA4/T0CKI	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)
7	RA5/AN4/SS#	I/O	Multiplexed I/O & Peripheral Pin RA5/AN4/SS# (General)
8	RE0/RD#/AN5	I/O	Multiplexed I/O & Peripheral Pin RE0/RD#/AN5 (General)
9	RE1/WR#/AN6	I/O	Multiplexed I/O & Peripheral Pin RE1/WR#/AN6 (General)
10	RE2/CS#/AN7	I/O	Multiplexed I/O & Peripheral Pin RE2/CS#/AN7 (General)
11	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
12	VSS	GND	Ground Reference Pin (VSS)
13	OSC1/CLKIN	I/O	Multiplexed I/O & Peripheral Pin OSC1/CLKIN (RTC/CLK)
14	OSC2/CLKOUT	I/O	Multiplexed I/O & Peripheral Pin OSC2/CLKOUT (RTC/CLK)
15	RC0/T1OSO/T1CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
16	RC1/T1OSI/CCP2	I/O	Multiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
17	RC2/CCP1	I/O	Multiplexed I/O & Peripheral Pin RC2/CCP1 (General)
18	RC3/SCK/SCL	I/O	Multiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
19	RD0/PSP0	I/O	Multiplexed I/O & Peripheral Pin RD0/PSP0 (General)
20	RD1/PSP1	I/O	Multiplexed I/O & Peripheral Pin RD1/PSP1 (General)
21	RD2/PSP2	I/O	Multiplexed I/O & Peripheral Pin RD2/PSP2 (General)
22	RD3/PSP3	I/O	Multiplexed I/O & Peripheral Pin RD3/PSP3 (General)
23	RC4/SDI/SDA	I/O	Multiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
24	RC5/SDO	I/O	Multiplexed I/O & Peripheral Pin RC5/SDO (General)
25	RC6/TX/CK	I/O	Multiplexed I/O & Peripheral Pin RC6/TX/CK (General)
26	RC7/RX/DT	I/O	Multiplexed I/O & Peripheral Pin RC7/RX/DT (General)
27	RD4/PSP4	I/O	Multiplexed I/O & Peripheral Pin RD4/PSP4 (General)
28	RD5/PSP5	I/O	Multiplexed I/O & Peripheral Pin RD5/PSP5 (General)
29	RD6/PSP6	I/O	Multiplexed I/O & Peripheral Pin RD6/PSP6 (General)
30	RD7/PSP7	I/O	Multiplexed I/O & Peripheral Pin RD7/PSP7 (General)
31	VSS	GND	Ground Reference Pin (VSS)
32	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
33	RB0/INT	I/O	Multiplexed I/O & Peripheral Pin RB0/INT (General)
34	RB1	I/O	Multiplexed I/O & Peripheral Pin RB1 (General)
35	RB2	I/O	Multiplexed I/O & Peripheral Pin RB2 (General)
36	RB3/PGM	I/O	Multiplexed I/O & Peripheral Pin RB3/PGM (General)
37	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
38	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
39	RB6/PGC	I/O	Multiplexed I/O & Peripheral Pin RB6/PGC (General)
40	RB7/PGD	I/O	Multiplexed I/O & Peripheral Pin RB7/PGD (General)

PIN 1 MCLR/VPP

I/O

Multiplexed I/O & Peripheral Pin MCLR/VPP (General)

Design note: MasterClear(Reset)inputorprogrammingvoltageinput . ThispinisanactivelowRESETtothedevice .

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16F877-04/P (PDIP-40) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16F877-04/P (PDIP-40) - 2. Standard Pinout (Top View)

True package pinout (40 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16F877-04/P (PDIP-40) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16F877-04/P (PDIP-40) - 4. Package Dimensions (D×E×A)

PDIP-40 · 10.00×10.00mm · Pitch 2.54mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16F877-04/P (PDIP-40) - 5. Recommended Land Pattern

IPC-7351B Footprint (40 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16F877-04/P (PDIP-40) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)

Showing 1–12 of 16 uncropped original figures for PIC16F877

P1 · p01_fig01EXACT PACKAGE

28/40-Pin 8-Bit CMOS FLASH Microcontrollers

P1 · p01_fig01P1

Datasheet Page 1 (p01_fig01)

P2 · p02_fig01834×893px

PLCC

P2 · p02_fig021149×890px

RC2/CCP1 RC3/SCK/SCL

P2 · p02_fig03852×894px

DS30292D-page 2  1998-2013 Microchip Technology Inc.

P59 · p59_fig01867×515px

FIGURE 8-1: CAPTURE MODE OPERATION BLOCK DIAGRAM RC2/CCP1

P60 · p60_fig01867×699px

PIC16F877-04/P (PDIP-40) — FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>).

FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>).

P134 · p134_fig01869×1162px

PIC16F877-04/P (PDIP-40) — Note 1: The High Voltage Programming mode is | always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. | 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a gen- eral purpose I/O pin

Note 1: The High Voltage Programming mode is | always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. | 2: While in Low Voltage ICSP mode, the RB3 pin can no longer be used as a gen- eral purpose I/O pin

P135 · p135_fig011778×1499px

FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0

P193 · p193_fig011442×1805px

PIC16F877-04/P (PDIP-40) — 15 10 5 15 10 5  Mold Draft Angle Bottom | 15 10 5 15 10 5  Mold Draft Angle Top | 17.27 16.51 15.75 .680 .650 .620 eB Overall Row Spacing § | 0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width | 1.78 1.27 0.76 .070 .050 .030 B1 Upper Lead

15 10 5 15 10 5  Mold Draft Angle Bottom | 15 10 5 15 10 5  Mold Draft Angle Top | 17.27 16.51 15.75 .680 .650 .620 eB Overall Row Spacing § | 0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width | 1.78 1.27 0.76 .070 .050 .030 B1 Upper Lead

P193 · p193_fig01P193

Datasheet Page 193 (p193_fig01)

P195 · p195_fig011442×1778px

PIC16F877-04/P (PDIP-40) — * Controlling Parameter | Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 | B | D1 | E | CH | 15 10 5 15

* Controlling Parameter | Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 | B | D1 | E | CH | 15 10 5 15

Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (PIC16F877-04/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16F877-04/P (PDIP-40) is a 40-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 3.85 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

20 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

10.00 × 10.00 × 3.85 mm (A1=0.51 mm)

Package family: DIP (PDIP-40)

Pin Count & Lead PitchN / e

40 Pins | Pitch e = 2.54 mm (100.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol40 auto-grouped pins

IPC-7351B Land Pattern40 pads · Pitch 2.54mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — PIC16F877 (2)

Select package variant or sibling MPN sharing this datasheet

PDIP-40 · 40P

PIC16F877-04/P

MICROCHIP·PDIP-40

IPC-7351B

40P10.0×10.0×3.85mmP=2.54mm

PIC16F877 (PDIP-40)

PLCC-44(16.6x16.6) · 44P

PIC16F877-20I/L

MICROCHIP·PLCC-44(16.6x16.6)

IPC-7351B

44P16.6×16.6×1.15mmP=1.27mm

PIC16F877 (PLCC-44(16.6x16.6))

Mechanical Dimensions & Land Pattern (PDIP-40)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 10.00 mm

Height (A) & Pitch (e)IPC-7351B

A=3.85mm · e=2.54mm

Pad Size (W × L)Level B

1.60 × 1.60 mm

Pins / Total PadsTopology

40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PDIP-40	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F877-04/P (PDIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F877-04/P (PDIP-40)?

Manufactured by MICROCHIP, the PIC16F877-04/P is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR/VPP: Multiplexed I/O & Peripheral Pin MCLR/VPP (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F877-04/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F877-04/P (PDIP-40) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F877-04/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F877-04/P (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & PIC16F877 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	MCLR/VPP	Digital_IO	Signal terminal MCLR/VPP (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR/VPP. Supported peripheral buses: General.
2	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
3	RA1/AN1	Digital_IO	Signal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
4	RA2/AN2/VREF	Analog	Signal terminal RA2/AN2/VREF (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF. Supported peripheral buses: General.
5	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
6	RA4/T0CKI	Digital_IO	Signal terminal RA4/T0CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
7	RA5/AN4/SS#	Digital_IO	Signal terminal RA5/AN4/SS# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/SS#. Supported peripheral buses: General.
8	RE0/RD#/AN5	Digital_IO	Signal terminal RE0/RD#/AN5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE0/RD#/AN5. Supported peripheral buses: General.
9	RE1/WR#/AN6	Digital_IO	Signal terminal RE1/WR#/AN6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE1/WR#/AN6. Supported peripheral buses: General.
10	RE2/CS#/AN7	Digital_IO	Signal terminal RE2/CS#/AN7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE2/CS#/AN7. Supported peripheral buses: General.
11	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
12	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13	OSC1/CLKIN	Digital_IO	Signal terminal OSC1/CLKIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
14	OSC2/CLKOUT	Digital_IO	Signal terminal OSC2/CLKOUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
15	RC0/T1OSO/T1CKI	Digital_IO	Signal terminal RC0/T1OSO/T1CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
16	RC1/T1OSI/CCP2	Digital_IO	Signal terminal RC1/T1OSI/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
17	RC2/CCP1	Digital_IO	Signal terminal RC2/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
18	RC3/SCK/SCL	Digital_IO	Signal terminal RC3/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
19	RD0/PSP0	Digital_IO	Signal terminal RD0/PSP0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD0/PSP0. Supported peripheral buses: General.
20	RD1/PSP1	Digital_IO	Signal terminal RD1/PSP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD1/PSP1. Supported peripheral buses: General.
21	RD2/PSP2	Digital_IO	Signal terminal RD2/PSP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD2/PSP2. Supported peripheral buses: General.
22	RD3/PSP3	Digital_IO	Signal terminal RD3/PSP3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD3/PSP3. Supported peripheral buses: General.
23	RC4/SDI/SDA	Digital_IO	Signal terminal RC4/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
24	RC5/SDO	Digital_IO	Signal terminal RC5/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
25	RC6/TX/CK	Digital_IO	Signal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
26	RC7/RX/DT	Digital_IO	Signal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
27	RD4/PSP4	Digital_IO	Signal terminal RD4/PSP4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD4/PSP4. Supported peripheral buses: General.
28	RD5/PSP5	Digital_IO	Signal terminal RD5/PSP5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD5/PSP5. Supported peripheral buses: General.
29	RD6/PSP6	Digital_IO	Signal terminal RD6/PSP6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD6/PSP6. Supported peripheral buses: General.
30	RD7/PSP7	Digital_IO	Signal terminal RD7/PSP7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD7/PSP7. Supported peripheral buses: General.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
33	RB0/INT	Digital_IO	Signal terminal RB0/INT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
34	RB1	Digital_IO	Signal terminal RB1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
35	RB2	Digital_IO	Signal terminal RB2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
36	RB3/PGM	Digital_IO	Signal terminal RB3/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/PGM. Supported peripheral buses: General.
37	RB4	Digital_IO	Signal terminal RB4 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
38	RB5	Digital_IO	Signal terminal RB5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
39	RB6/PGC	Digital_IO	Signal terminal RB6/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/PGC. Supported peripheral buses: General.
40	RB7/PGD	Digital_IO	Signal terminal RB7/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/PGD. Supported peripheral buses: General.

4D Studio: PIC16F877-04/P Permalink: /part/C220174 MICROCHIP PDIP-40 All Packages All Manufacturers