AT42QT1110-AUR (TQFP-32(7x7)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of AT42QT1110-AUR (TQFP-32(7x7))?

Manufactured by MICROCHIP, the AT42QT1110-AUR is housed in a TQFP-32(7x7) package with 32 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 3 V – 5.5 V. Key pins include: 1 (SNS0K: Multiplexed I/O & Peripheral Pin SNS0K (General)), 2 (SNS1: Multiplexed I/O & Peripheral Pin SNS1 (General)), 3 (SNS1K: Multiplexed I/O & Peripheral Pin SNS1K (General)), 4 (Vdd: Power Supply Input (Vdd — 3 V – 5.5 V)), 5 (Vss: Ground Reference Pin (Vss)), 6 (SNS2K: Multiplexed I/O & Peripheral Pin SNS2K (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for AT42QT1110-AUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT1110-AUR (TQFP-32(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.80 mm, and 32 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT1110-AUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT1110-AUR (MICROCHIP, TQFP-32(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 7.00mm × 7.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	SNS0K	I/O	Multiplexed I/O & Peripheral Pin SNS0K (General)
2	SNS1	I/O	Multiplexed I/O & Peripheral Pin SNS1 (General)
3	SNS1K	I/O	Multiplexed I/O & Peripheral Pin SNS1K (General)
4	Vdd	Power	Power Supply Input (Vdd — 3 V – 5.5 V)
5	Vss	GND	Ground Reference Pin (Vss)
6	SNS2K	I/O	Multiplexed I/O & Peripheral Pin SNS2K (General)
7	SNS2	I/O	Multiplexed I/O & Peripheral Pin SNS2 (General)
8	SNS3	I/O	Multiplexed I/O & Peripheral Pin SNS3 (General)
9	SNS3K	I/O	Multiplexed I/O & Peripheral Pin SNS3K (General)
10	SNS4	I/O	Multiplexed I/O & Peripheral Pin SNS4 (General)
11	SNS4K	I/O	Multiplexed I/O & Peripheral Pin SNS4K (General)
12	SNS5	I/O	Multiplexed I/O & Peripheral Pin SNS5 (General)
13	SNS5K	I/O	Multiplexed I/O & Peripheral Pin SNS5K (General)
14	SS	I/O	Multiplexed I/O & Peripheral Pin SS (General)
15	MOSI	I/O	Multiplexed I/O & Peripheral Pin MOSI (SPI)
16	MISO	I/O	Multiplexed I/O & Peripheral Pin MISO (SPI)
17	SCK	I/O	Multiplexed I/O & Peripheral Pin SCK (SPI)
18	Vdd	Power	Power Supply Input (Vdd — 3 V – 5.5 V)
19	SNS6K	I/O	Multiplexed I/O & Peripheral Pin SNS6K (General)
20	SNS6	I/O	Multiplexed I/O & Peripheral Pin SNS6 (General)
21	Vss	GND	Ground Reference Pin (Vss)
22	SNS7K/DETECT0	I/O	Multiplexed I/O & Peripheral Pin SNS7K/DETECT0 (General)
23	SNS7/DETECT1	I/O	Multiplexed I/O & Peripheral Pin SNS7/DETECT1 (General)
24	SNS8/DETECT2	I/O	Multiplexed I/O & Peripheral Pin SNS8/DETECT2 (General)
25	SNS8K/DETECT3	I/O	Multiplexed I/O & Peripheral Pin SNS8K/DETECT3 (General)
26	SNS9/DETECT4	I/O	Multiplexed I/O & Peripheral Pin SNS9/DETECT4 (General)
27	SNS9K/DETECT5	I/O	Multiplexed I/O & Peripheral Pin SNS9K/DETECT5 (General)
28	CHANGE	I/O	Multiplexed I/O & Peripheral Pin CHANGE (General)
29	RESET	I	System Enable & Hardware Reset (RESET)
30	SNS10/DETECT6	I/O	Multiplexed I/O & Peripheral Pin SNS10/DETECT6 (General)
31	SNS10K/SYNC	I/O	Multiplexed I/O & Peripheral Pin SNS10K/SYNC (General)
32	SNS0	I/O	Multiplexed I/O & Peripheral Pin SNS0 (General)

PIN 1 SNS0K

I/O

Multiplexed I/O & Peripheral Pin SNS0K (General)

Design note: Signal terminal SNS0K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS0K. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

AT42QT1110-AUR (TQFP-32(7x7)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

AT42QT1110-AUR (TQFP-32(7x7)) - 2. Standard Pinout (Top View)

True package pinout (32 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

AT42QT1110-AUR (TQFP-32(7x7)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

AT42QT1110-AUR (TQFP-32(7x7)) - 4. Package Dimensions (D×E×A)

TQFP-32(7x7) · 7.00×7.00mm · Pitch 0.80mmExpand ›

5. Recommended Land PatternLAND PATTERN

AT42QT1110-AUR (TQFP-32(7x7)) - 5. Recommended Land Pattern

IPC-7351B Footprint (32 Pads)Expand ›

6. Application SchematicSCHEMATIC

AT42QT1110-AUR (TQFP-32(7x7)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)

Showing 1–4 of 4 uncropped original figures for AT42QT1110

P42 · p42_fig01EXACT PACKAGE

42 AT42QT1110-MU / AT42QT1110-AU [DATASHEET]

P2 · p02_fig011023×1023px

1.1 Pinout Configuration

P2 · p02_fig01P2

Datasheet Page 2 (p02_fig01)

P42 · p42_fig01P42

Datasheet Page 42 (p42_fig01)

Technical Specifications & Part Details (AT42QT1110-AUR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:AT42QT1110-AUR (TQFP-32(7x7)) is a 32-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3 V – 5.5 V supply operation across 40°C to +85°C with integrated SPI interfaces.

Operating Supply VoltageV_CC / V_DD

3 V – 5.5 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1.5 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

7.00 × 7.00 × 1.20 mm (A1=0.10 mm)

Package family: TQFP (TQFP-32(7x7))

Pin Count & Lead PitchN / e

32 Pins | Pitch e = 0.80 mm (31.5 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol32 auto-grouped pins

IPC-7351B Land Pattern32 pads · Pitch 0.80mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-32(7x7))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

7.00 × 7.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.80mm

Pad Size (W × L)Level B

0.50 × 1.50 mm

Pins / Total PadsTopology

32P / 32Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TQFP-32(7x7)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT42QT1110-AUR (TQFP-32(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT42QT1110-AUR (TQFP-32(7x7))?

Manufactured by MICROCHIP, the AT42QT1110-AUR is housed in a TQFP-32(7x7) package with 32 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 3 V – 5.5 V. Key pins include: 1 (SNS0K: Multiplexed I/O & Peripheral Pin SNS0K (General)), 2 (SNS1: Multiplexed I/O & Peripheral Pin SNS1 (General)), 3 (SNS1K: Multiplexed I/O & Peripheral Pin SNS1K (General)), 4 (Vdd: Power Supply Input (Vdd — 3 V – 5.5 V)), 5 (Vss: Ground Reference Pin (Vss)), 6 (SNS2K: Multiplexed I/O & Peripheral Pin SNS2K (General)).

What are the IPC-7351B PCB Footprint dimensions for AT42QT1110-AUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT1110-AUR (TQFP-32(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.80 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT1110-AUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT1110-AUR (MICROCHIP, TQFP-32(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & AT42QT1110 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	SNS0K	Digital_IO	Signal terminal SNS0K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS0K. Supported peripheral buses: General.
2	SNS1	Digital_IO	Signal terminal SNS1 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS1. Supported peripheral buses: General.
3	SNS1K	Digital_IO	Signal terminal SNS1K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS1K. Supported peripheral buses: General.
4	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 3 V – 5.5 V domain (Max rating: 5.5V).
5	Vss	GND	0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
6	SNS2K	Digital_IO	Signal terminal SNS2K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS2K. Supported peripheral buses: General.
7	SNS2	Digital_IO	Signal terminal SNS2 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS2. Supported peripheral buses: General.
8	SNS3	Digital_IO	Signal terminal SNS3 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS3. Supported peripheral buses: General.
9	SNS3K	Digital_IO	Signal terminal SNS3K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS3K. Supported peripheral buses: General.
10	SNS4	Digital_IO	Signal terminal SNS4 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS4. Supported peripheral buses: General.
11	SNS4K	Digital_IO	Signal terminal SNS4K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS4K. Supported peripheral buses: General.
12	SNS5	Digital_IO	Signal terminal SNS5 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS5. Supported peripheral buses: General.
13	SNS5K	Digital_IO	Signal terminal SNS5K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS5K. Supported peripheral buses: General.
14	SS	Digital_IO	Signal terminal SS (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SS. Supported peripheral buses: General.
15	MOSI	Digital_IO	Signal terminal MOSI (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: MOSI. Supported peripheral buses: SPI.
16	MISO	Digital_IO	Signal terminal MISO (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: MISO. Supported peripheral buses: SPI.
17	SCK	Digital_IO	Signal terminal SCK (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
18	Vdd	Power_In	Primary positive power supply input (Vdd) operating in the 3 V – 5.5 V domain (Max rating: 5.5V).
19	SNS6K	Digital_IO	Signal terminal SNS6K (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS6K. Supported peripheral buses: General.
20	SNS6	Digital_IO	Signal terminal SNS6 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS6. Supported peripheral buses: General.
21	Vss	GND	0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
22	SNS7K/DETECT0	Digital_IO	Signal terminal SNS7K/DETECT0 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS7K/DETECT0. Supported peripheral buses: General.
23	SNS7/DETECT1	Digital_IO	Signal terminal SNS7/DETECT1 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS7/DETECT1. Supported peripheral buses: General.
24	SNS8/DETECT2	Digital_IO	Signal terminal SNS8/DETECT2 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS8/DETECT2. Supported peripheral buses: General.
25	SNS8K/DETECT3	Digital_IO	Signal terminal SNS8K/DETECT3 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS8K/DETECT3. Supported peripheral buses: General.
26	SNS9/DETECT4	Digital_IO	Signal terminal SNS9/DETECT4 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS9/DETECT4. Supported peripheral buses: General.
27	SNS9K/DETECT5	Digital_IO	Signal terminal SNS9K/DETECT5 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS9K/DETECT5. Supported peripheral buses: General.
28	CHANGE	Digital_IO	Signal terminal CHANGE (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: CHANGE. Supported peripheral buses: General.
29	RESET	Digital_IO	Active-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
30	SNS10/DETECT6	Digital_IO	Signal terminal SNS10/DETECT6 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS10/DETECT6. Supported peripheral buses: General.
31	SNS10K/SYNC	Digital_IO	Signal terminal SNS10K/SYNC (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS10K/SYNC. Supported peripheral buses: General.
32	SNS0	Digital_IO	Signal terminal SNS0 (I/O, 3 V – 5.5 V domain). Multiplexed alternate functions: SNS0. Supported peripheral buses: General.

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