PIC24F16KL402-I/ML (QFN-28-EP(6x6)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC24F16KL402-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24F16KL402-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (ANA: Multiplexed I/O & Peripheral Pin ANA (General)), 2 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 3 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 4 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 5 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 6 (—: Multiplexed I/O & Peripheral Pin — (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC24F16KL402-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24F16KL402-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24F16KL402-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24F16KL402-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	ANA	I/O	Multiplexed I/O & Peripheral Pin ANA (General)
2	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
3	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
4	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
5	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
6	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
7	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
8	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
9	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
10	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
11	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
12	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
13	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
14	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
15	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
16	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
17	—	I/O	Multiplexed I/O & Peripheral Pin — (General)
18	ST	I/O	Multiplexed I/O & Peripheral Pin ST (General)
19	ANA	I/O	Multiplexed I/O & Peripheral Pin ANA (General)
20	ANA	I/O	Multiplexed I/O & Peripheral Pin ANA (General)
21	AN11/SDO1/CN13/RB13	I/O	Multiplexed I/O & Peripheral Pin AN11/SDO1/CN13/RB13 (General)
22	IO11	I/O	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	I/O	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	VSS	GND	Ground Reference Pin (VSS)
25	VDD	Power	Power Supply Input (VDD — 1.8V to 3.6V)
26	MCLR#/VPP/RA5	I/O	Multiplexed I/O & Peripheral Pin MCLR#/VPP/RA5 (General)
27	IO47	I/O	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	IO33	I/O	GPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29	EP	GND	Exposed Thermal & Ground Pad (EP)

PIN 1 ANA

I/O

Multiplexed I/O & Peripheral Pin ANA (General)

Design note: ULPWU

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)

True package pinout (29 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)

QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern

IPC-7351B Footprint (29 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)

Showing 1–8 of 8 uncropped original figures for PIC24F16KL40

P1 · p01_fig01377×200px

Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with XLP Technology

P13 · p13_fig011544×2097px

FIGURE 1-1: PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM

P22 · p22_fig01867×940px

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

P22 · p22_fig01P22

Datasheet Page 22 (p22_fig01)

P47 · p47_fig011397×783px

FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS

P225 · p225_fig011777×2364px

27.1 Package Marking Information

P248 · p248_fig011777×2734px

PIC24F16KL402-I/ML (QFN-28-EP(6x6)) — PIC24F16KL402 FAMILY | DS30001037C-page 248  2011-2013 Microchip Technology Inc. | 28-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length | Note: For the most current package drawings,

PIC24F16KL402 FAMILY | DS30001037C-page 248  2011-2013 Microchip Technology Inc. | 28-Lead Plastic Quad Flat, No Lead Package (MQ) - 5x5 mm Body [QFN] Land Pattern With 0.55 mm Contact Length | Note: For the most current package drawings,

P248 · p248_fig01P248

Datasheet Page 248 (p248_fig01)

Technical Specifications & Part Details (PIC24F16KL402-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC24F16KL402-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, IrDA interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

6.00 × 6.00 × 1.00 mm (A1=0.03 mm)

Package family: QFN (QFN-28-EP(6x6))

Pin Count & Lead PitchN / e

28 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, IrDA

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol29 auto-grouped pins

IPC-7351B Land Pattern29 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

6.00 × 6.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.00mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-28-EP(6x6)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24F16KL402-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24F16KL402-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24F16KL402-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (ANA: Multiplexed I/O & Peripheral Pin ANA (General)), 2 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 3 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 4 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 5 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 6 (—: Multiplexed I/O & Peripheral Pin — (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24F16KL402-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24F16KL402-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24F16KL402-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24F16KL402-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC24F16KL40 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	ANA	Digital_IO	Signal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
2	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
3	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
4	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
5	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
6	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U2RTS. Supported peripheral buses: General.
7	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U2CTS. Supported peripheral buses: General.
8	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
9	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1CTS. Supported peripheral buses: General.
10	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General.
11	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
12	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
13	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
14	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
15	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
16	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
17	—	Digital_IO	Signal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
18	ST	Digital_IO	Signal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
19	ANA	Digital_IO	Signal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
20	ANA	Digital_IO	Signal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
21	AN11/SDO1/CN13/RB13	Digital_IO	Signal terminal AN11/SDO1/CN13/RB13 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: AN11/SDO1/CN13/RB13. Supported peripheral buses: General.
22	IO11	Digital_IO	GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23	IO12	Digital_IO	GPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	VDD	Power_In	Primary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
26	MCLR#/VPP/RA5	Digital_IO	Signal terminal MCLR#/VPP/RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: MCLR#/VPP/RA5. Supported peripheral buses: General.
27	IO47	Digital_IO	GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28	IO33	Digital_IO	GPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29	EP	GND	Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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