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PIC18LF47K40-E/PT (TQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18LF47K40-E/PT

MICROCHIPID: C219298TQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18LF47K40-E/PT (TQFP-44(10x10))1IOCEN[n]=12RD43RD54RD65RD76VSS7Vdd8RB09RB110RB211RB312NC13NC14RB415RB516ICSPCLK/RB617ICSPDAT/RB718VPP/#MCLR/RE19RA020RA121RA222RA344RC643RC542RC441RD340RD239RD138RD037RC336RC235RC134NC33NC32RC031RA630RA729Vss28Vdd27RE226RE125RE024RA523RA4Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IOCEN[n]=1I/OMultiplexed I/O & Peripheral Pin IOCEN[n]=1 (General)
2RD4I/OMultiplexed I/O & Peripheral Pin RD4 (General)
3RD5I/OMultiplexed I/O & Peripheral Pin RD5 (General)
4RD6I/OMultiplexed I/O & Peripheral Pin RD6 (General)
5RD7I/OMultiplexed I/O & Peripheral Pin RD7 (General)
6VSSGNDGround Reference Pin (VSS)
7VddPowerPower Supply Input (Vdd — 1.8V to 3.6V)
8RB0I/OMultiplexed I/O & Peripheral Pin RB0 (General)
9RB1I/OMultiplexed I/O & Peripheral Pin RB1 (General)
10RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
11RB3I/OMultiplexed I/O & Peripheral Pin RB3 (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
15RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
16ICSPCLK/RB6I/OMultiplexed I/O & Peripheral Pin ICSPCLK/RB6 (General)
17ICSPDAT/RB7I/OMultiplexed I/O & Peripheral Pin ICSPDAT/RB7 (General)
18VPP/#MCLR/RE3I/OMultiplexed I/O & Peripheral Pin VPP/#MCLR/RE3 (General)
19RA0I/OMultiplexed I/O & Peripheral Pin RA0 (General)
20RA1I/OMultiplexed I/O & Peripheral Pin RA1 (General)
21RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
22RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
23RA4I/OMultiplexed I/O & Peripheral Pin RA4 (General)
24RA5I/OMultiplexed I/O & Peripheral Pin RA5 (General)
25RE0I/OMultiplexed I/O & Peripheral Pin RE0 (General)
26RE1I/OMultiplexed I/O & Peripheral Pin RE1 (General)
27RE2I/OMultiplexed I/O & Peripheral Pin RE2 (General)
28VddPowerPower Supply Input (Vdd — 1.8V to 3.6V)
29VssGNDGround Reference Pin (Vss)
30RA7I/OMultiplexed I/O & Peripheral Pin RA7 (General)
31RA6I/OMultiplexed I/O & Peripheral Pin RA6 (General)
32RC0I/OMultiplexed I/O & Peripheral Pin RC0 (General)
33NCI/OMultiplexed I/O & Peripheral Pin NC (General)
34NCI/OMultiplexed I/O & Peripheral Pin NC (General)
35RC1I/OMultiplexed I/O & Peripheral Pin RC1 (General)
36RC2I/OMultiplexed I/O & Peripheral Pin RC2 (General)
37RC3I/OMultiplexed I/O & Peripheral Pin RC3 (General)
38RD0I/OMultiplexed I/O & Peripheral Pin RD0 (General)
39RD1I/OMultiplexed I/O & Peripheral Pin RD1 (General)
40RD2I/OMultiplexed I/O & Peripheral Pin RD2 (General)
41RD3I/OMultiplexed I/O & Peripheral Pin RD3 (General)
42RC4I/OMultiplexed I/O & Peripheral Pin RC4 (General)
43RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
44RC6I/OMultiplexed I/O & Peripheral Pin RC6 (General)
PIN 1 IOCEN[n]=1
I/O
Multiplexed I/O & Peripheral Pin IOCEN[n]=1 (General)
Design note: Signal terminal IOCEN[n]=1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: IOCEN[n]=1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC18LF47K40-E/PT (MICROCHIP · TQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18LF47K40-E/PT (TQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for PIC18LF47K40
P1 · p01_fig01EXACT PACKAGE
PIC18LF47K40-E/PT (TQFP-44(10x10)) — 28/40/44-Pin, Low-Power, High-Performance
28/40/44-Pin, Low-Power, High-Performance
P793 · p793_fig01EXACT PACKAGE
PIC18LF47K40-E/PT (TQFP-44(10x10)) — 44-Lead QFN (8x8x0.9 mm) Example
44-Lead QFN (8x8x0.9 mm) Example
P30 · p30_fig01585×438px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Figure 2-2. Example of MCLR Pin Connections
Figure 2-2. Example of MCLR Pin Connections
P83 · p83_fig011778×711px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Figure 6-3. WAKE-UP FROM SLEEP THROUGH INTERRUPT
Figure 6-3. WAKE-UP FROM SLEEP THROUGH INTERRUPT
P290 · p290_fig011775×1546px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — 16.4 Enabling the Module
16.4 Enabling the Module
P372 · p372_fig01930×595px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Figure 21-2. Compare Mode Operation Block Diagram
Figure 21-2. Compare Mode Operation Block Diagram
P442 · p442_fig011469×1318px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Figure 26-1. MSSP Block Diagram (SPI mode)
Figure 26-1. MSSP Block Diagram (SPI mode)
P444 · p444_fig011705×878px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Figure 26-3. SPI Master/Slave Connection
Figure 26-3. SPI Master/Slave Connection
P444 · p444_fig01P444
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Datasheet Page 444 (p444_fig01)
Datasheet Page 444 (p444_fig01)
P793 · p793_fig01P793
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Datasheet Page 793 (p793_fig01)
Datasheet Page 793 (p793_fig01)
P809 · p809_fig011195×1351px
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Contact Pad Length (X44) Contact Pad Width (X44)
Contact Pad Length (X44) Contact Pad Width (X44)
P809 · p809_fig01P809
PIC18LF47K40-E/PT (TQFP-44(10x10)) — Datasheet Page 809 (p809_fig01)
Datasheet Page 809 (p809_fig01)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC18LF47K40-E/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18LF47K40-E/PT (TQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V to 3.6V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, DAC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
64 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18LF47K40-E/PT (TQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18LF47K40-E/PT (TQFP-44(10x10))?

Manufactured by MICROCHIP, the PIC18LF47K40-E/PT is housed in a TQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (IOCEN[n]=1: Multiplexed I/O & Peripheral Pin IOCEN[n]=1 (General)), 2 (RD4: Multiplexed I/O & Peripheral Pin RD4 (General)), 3 (RD5: Multiplexed I/O & Peripheral Pin RD5 (General)), 4 (RD6: Multiplexed I/O & Peripheral Pin RD6 (General)), 5 (RD7: Multiplexed I/O & Peripheral Pin RD7 (General)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for PIC18LF47K40-E/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18LF47K40-E/PT (TQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18LF47K40-E/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18LF47K40-E/PT (MICROCHIP, TQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & PIC18LF47K40 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IOCEN[n]=1Digital_IOSignal terminal IOCEN[n]=1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: IOCEN[n]=1. Supported peripheral buses: General.
2RD4Digital_IOSignal terminal RD4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD4. Supported peripheral buses: General.
3RD5Digital_IOSignal terminal RD5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD5. Supported peripheral buses: General.
4RD6Digital_IOSignal terminal RD6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD6. Supported peripheral buses: General.
5RD7Digital_IOSignal terminal RD7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD7. Supported peripheral buses: General.
6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
8RB0Digital_IOSignal terminal RB0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
9RB1Digital_IOSignal terminal RB1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
10RB2Digital_IOSignal terminal RB2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
11RB3Digital_IOSignal terminal RB3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14RB4Digital_IOSignal terminal RB4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
15RB5Digital_IOSignal terminal RB5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
16ICSPCLK/RB6Digital_IOSignal terminal ICSPCLK/RB6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ICSPCLK/RB6. Supported peripheral buses: General.
17ICSPDAT/RB7Digital_IOSignal terminal ICSPDAT/RB7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ICSPDAT/RB7. Supported peripheral buses: General.
18VPP/#MCLR/RE3Digital_IOSignal terminal VPP/#MCLR/RE3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: VPP/#MCLR/RE3. Supported peripheral buses: General.
19RA0Digital_IOSignal terminal RA0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
20RA1Digital_IOSignal terminal RA1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
21RA2Digital_IOSignal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
22RA3Digital_IOSignal terminal RA3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
23RA4Digital_IOSignal terminal RA4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
24RA5Digital_IOSignal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
25RE0Digital_IOSignal terminal RE0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RE0. Supported peripheral buses: General.
26RE1Digital_IOSignal terminal RE1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RE1. Supported peripheral buses: General.
27RE2Digital_IOSignal terminal RE2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RE2. Supported peripheral buses: General.
28VddPower_InPrimary positive power supply input (Vdd) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
29VssGND0V electrical ground return terminal (Vss) for internal core logic, I/O drivers, and analog sub-blocks.
30RA7Digital_IOSignal terminal RA7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
31RA6Digital_IOSignal terminal RA6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
32RC0Digital_IOSignal terminal RC0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
33NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
34NCNCSignal terminal NC (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
35RC1Digital_IOSignal terminal RC1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
36RC2Digital_IOSignal terminal RC2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
37RC3Digital_IOSignal terminal RC3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
38RD0Digital_IOSignal terminal RD0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD0. Supported peripheral buses: General.
39RD1Digital_IOSignal terminal RD1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD1. Supported peripheral buses: General.
40RD2Digital_IOSignal terminal RD2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD2. Supported peripheral buses: General.
41RD3Digital_IOSignal terminal RD3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RD3. Supported peripheral buses: General.
42RC4Digital_IOSignal terminal RC4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
43RC5Digital_IOSignal terminal RC5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
44RC6Digital_IOSignal terminal RC6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
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