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ENC624J600-I/PT (TQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ENC624J600-I/PT

MICROCHIPID: C219176TQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ENC624J600-I/PT (TQFP-64(10x10))1PSPMode102OSC23OSC14VDDOSC5AD46AD57AD68AD79LEDB10LEDA11RBIAS12VDDPLL13VSSPLL14VSSRX15VDDRX16TPIN+17TPIN -18VDDTX19VSSTX20TPOUT+21TPOUT -22VSSTX23CLKOUT24SPISEL25AD826AD927AD1028AD1129AD1230AD1331AD1432PSPCFG064VDD63VCAP62VSS61A460A359A258A157A056AD355AD254AD153AD052SCK/AL/PSPCF51SI/RD/RW50SO/WR/WRL/EN49CS#/CS48WRH/B1SEL47VDD46VSS45A14/PSPCFG144VDD43VCAP42VSS41AD340AD239AD138AD037SCK36SI35WR34CS33VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PSPMode10I/OMultiplexed I/O & Peripheral Pin PSPMode10 (General)
2OSC2I/OMultiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)
3OSC1I/OMultiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)
4VDDOSCPowerPower Supply Input (VDDOSC — 3.0V to 3.6V)
5AD4I/OMultiplexed I/O & Peripheral Pin AD4 (General)
6AD5I/OMultiplexed I/O & Peripheral Pin AD5 (General)
7AD6I/OMultiplexed I/O & Peripheral Pin AD6 (General)
8AD7I/OMultiplexed I/O & Peripheral Pin AD7 (General)
9LEDBI/OMultiplexed I/O & Peripheral Pin LEDB (General)
10LEDAI/OMultiplexed I/O & Peripheral Pin LEDA (General)
11RBIASI/OMultiplexed I/O & Peripheral Pin RBIAS (General)
12VDDPLLPowerPower Supply Input (VDDPLL — 3.0V to 3.6V)
13VSSPLLGNDGround Reference Pin (VSSPLL)
14VSSRXGNDGround Reference Pin (VSSRX)
15VDDRXPowerPower Supply Input (VDDRX — 3.0V to 3.6V)
16TPIN+I/OMultiplexed I/O & Peripheral Pin TPIN+ (General)
17TPIN -I/OMultiplexed I/O & Peripheral Pin TPIN - (General)
18VDDTXPowerPower Supply Input (VDDTX — 3.0V to 3.6V)
19VSSTXGNDGround Reference Pin (VSSTX)
20TPOUT+I/OMultiplexed I/O & Peripheral Pin TPOUT+ (General)
21TPOUT -I/OMultiplexed I/O & Peripheral Pin TPOUT - (General)
22VSSTXGNDGround Reference Pin (VSSTX)
23CLKOUTI/OMultiplexed I/O & Peripheral Pin CLKOUT (General)
24SPISELI/OMultiplexed I/O & Peripheral Pin SPISEL (SPI)
25AD8I/OMultiplexed I/O & Peripheral Pin AD8 (General)
26AD9I/OMultiplexed I/O & Peripheral Pin AD9 (General)
27AD10I/OMultiplexed I/O & Peripheral Pin AD10 (General)
28AD11I/OMultiplexed I/O & Peripheral Pin AD11 (General)
29AD12I/OMultiplexed I/O & Peripheral Pin AD12 (General)
30AD13I/OMultiplexed I/O & Peripheral Pin AD13 (General)
31AD14I/OMultiplexed I/O & Peripheral Pin AD14 (General)
32PSPCFG0I/OMultiplexed I/O & Peripheral Pin PSPCFG0 (General)
33VSSGNDGround Reference Pin (VSS)
34CSI/OMultiplexed I/O & Peripheral Pin CS (General)
35WRI/OMultiplexed I/O & Peripheral Pin WR (General)
36SII/OMultiplexed I/O & Peripheral Pin SI (SPI)
37SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
38AD0I/OMultiplexed I/O & Peripheral Pin AD0 (General)
39AD1I/OMultiplexed I/O & Peripheral Pin AD1 (General)
40AD2I/OMultiplexed I/O & Peripheral Pin AD2 (General)
41AD3I/OMultiplexed I/O & Peripheral Pin AD3 (General)
42VSSGNDGround Reference Pin (VSS)
43VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
44VDDPowerPower Supply Input (VDD — 3.0V to 3.6V)
45A14/PSPCFG1I/OMultiplexed I/O & Peripheral Pin A14/PSPCFG1 (General)
46VSSGNDGround Reference Pin (VSS)
47VDDPowerPower Supply Input (VDD — 3.0V to 3.6V)
48WRH/B1SELI/OMultiplexed I/O & Peripheral Pin WRH/B1SEL (General)
49CS#/CSI/OMultiplexed I/O & Peripheral Pin CS#/CS (General)
50SO/WR/WRL/EN/B0SELI/OMultiplexed I/O & Peripheral Pin SO/WR/WRL/EN/B0SEL (General)
51SI/RD/RWI/OMultiplexed I/O & Peripheral Pin SI/RD/RW (General)
52SCK/AL/PSPCFG4I/OMultiplexed I/O & Peripheral Pin SCK/AL/PSPCFG4 (SPI)
53AD0I/OMultiplexed I/O & Peripheral Pin AD0 (General)
54AD1I/OMultiplexed I/O & Peripheral Pin AD1 (General)
55AD2I/OMultiplexed I/O & Peripheral Pin AD2 (General)
56AD3I/OMultiplexed I/O & Peripheral Pin AD3 (General)
57A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
58A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
59A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
60A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
61A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
62VSSGNDGround Reference Pin (VSS)
63VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
64VDDPowerPower Supply Input (VDD — 3.0V to 3.6V)
PIN 1 PSPMode10
I/O
Multiplexed I/O & Peripheral Pin PSPMode10 (General)
Design note: Signal terminal PSPMode10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPMode10. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ENC624J600-I/PT (MICROCHIP · TQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ENC624J600-I/PT (TQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ENC624J600-I/PT (TQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ENC624J600-I/PT (TQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ENC624J600-I/PT (TQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ENC624J600-I/PT (TQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
ENC624J600-I/PT (TQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for ENC624
P2 · p02_fig011777×1640px
ENC624J600-I/PT (TQFP-64(10x10)) — DS39935C-page ii  2010 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In
DS39935C-page ii  2010 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In
P2 · p02_fig02786×285px
ENC624J600-I/PT (TQFP-64(10x10)) — DS39935C-page ii  2010 Microchip Technology Inc.
DS39935C-page ii  2010 Microchip Technology Inc.
P13 · p13_fig011777×1210px
ENC624J600-I/PT (TQFP-64(10x10)) — FIGURE 2-5: TYPICAL ETHERNET MAGNETICS CONNECTIONS
FIGURE 2-5: TYPICAL ETHERNET MAGNETICS CONNECTIONS
P13 · p13_fig01P13
ENC624J600-I/PT (TQFP-64(10x10)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P14 · p14_fig011777×490px
ENC624J600-I/PT (TQFP-64(10x10)) — FIGURE 2-6: ALTERNATE TX CHOKE TOPOLOGY
FIGURE 2-6: ALTERNATE TX CHOKE TOPOLOGY
P14 · p14_fig02867×352px
ENC624J600-I/PT (TQFP-64(10x10)) — FIGURE 2-8: BI-COLOR LED CONNECTION
FIGURE 2-8: BI-COLOR LED CONNECTION
P151 · p151_fig02428×1530px
ENC624J600-I/PT (TQFP-64(10x10)) — ENC424J600 | Example | -I/ML | 1010017 | Example | ENC424J600 -I/PT | 1010017 | Example | ENC624J600 -I/PT | 1010017 | 3 e | 3 e | 3 e
ENC424J600 | Example | -I/ML | 1010017 | Example | ENC424J600 -I/PT | 1010017 | Example | ENC624J600 -I/PT | 1010017 | 3 e | 3 e | 3 e
P151 · p151_fig031777×756px
ENC624J600-I/PT (TQFP-64(10x10)) —  2010 Microchip Technology Inc. DS39935C-page 149 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe
 2010 Microchip Technology Inc. DS39935C-page 149 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe
P151 · p151_fig03P151
ENC624J600-I/PT (TQFP-64(10x10)) — Datasheet Page 151 (p151_fig03)
Datasheet Page 151 (p151_fig03)
P151 · p151_fig01All Packages in PDF
ENC624J600-I/PT (TQFP-64(10x10)) — 18.1 Package Marking Information
18.1 Package Marking Information

Technical Specifications & Part Details (ENC624J600-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ENC624J600-I/PT (TQFP-64(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +85°C with integrated SPI, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ENC624J600-I/PT (TQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ENC624J600-I/PT (TQFP-64(10x10))?

Manufactured by MICROCHIP, the ENC624J600-I/PT is housed in a TQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (PSPMode10: Multiplexed I/O & Peripheral Pin PSPMode10 (General)), 2 (OSC2: Multiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)), 3 (OSC1: Multiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)), 4 (VDDOSC: Power Supply Input (VDDOSC — 3.0V to 3.6V)), 5 (AD4: Multiplexed I/O & Peripheral Pin AD4 (General)), 6 (AD5: Multiplexed I/O & Peripheral Pin AD5 (General)).

What are the IPC-7351B PCB Footprint dimensions for ENC624J600-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ENC624J600-I/PT (TQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ENC624J600-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ENC624J600-I/PT (MICROCHIP, TQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & ENC624 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PSPMode10Digital_IOSignal terminal PSPMode10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPMode10. Supported peripheral buses: General.
2OSC2Digital_IOSignal terminal OSC2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2. Supported peripheral buses: RTC/CLK.
3OSC1Digital_IOSignal terminal OSC1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1. Supported peripheral buses: RTC/CLK.
4VDDOSCPower_InPrimary positive power supply input (VDDOSC) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
5AD4Digital_IOSignal terminal AD4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD4. Supported peripheral buses: General.
6AD5Digital_IOSignal terminal AD5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD5. Supported peripheral buses: General.
7AD6Digital_IOSignal terminal AD6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD6. Supported peripheral buses: General.
8AD7Digital_IOSignal terminal AD7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD7. Supported peripheral buses: General.
9LEDBDigital_IOSignal terminal LEDB (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: LEDB. Supported peripheral buses: General.
10LEDADigital_IOSignal terminal LEDA (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: LEDA. Supported peripheral buses: General.
11RBIASDigital_IOSignal terminal RBIAS (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RBIAS. Supported peripheral buses: General.
12VDDPLLPower_InPrimary positive power supply input (VDDPLL) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
13VSSPLLGND0V electrical ground return terminal (VSSPLL) for internal core logic, I/O drivers, and analog sub-blocks.
14VSSRXGND0V electrical ground return terminal (VSSRX) for internal core logic, I/O drivers, and analog sub-blocks.
15VDDRXPower_InPrimary positive power supply input (VDDRX) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
16TPIN+Digital_IOSignal terminal TPIN+ (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPIN+. Supported peripheral buses: General.
17TPIN -Digital_IOSignal terminal TPIN - (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPIN -. Supported peripheral buses: General.
18VDDTXPower_InPrimary positive power supply input (VDDTX) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
19VSSTXGND0V electrical ground return terminal (VSSTX) for internal core logic, I/O drivers, and analog sub-blocks.
20TPOUT+Digital_IOSignal terminal TPOUT+ (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPOUT+. Supported peripheral buses: General.
21TPOUT -Digital_IOSignal terminal TPOUT - (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPOUT -. Supported peripheral buses: General.
22VSSTXGND0V electrical ground return terminal (VSSTX) for internal core logic, I/O drivers, and analog sub-blocks.
23CLKOUTDigital_IOSignal terminal CLKOUT (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: CLKOUT. Supported peripheral buses: General.
24SPISELDigital_IOSignal terminal SPISEL (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
25AD8Digital_IOSignal terminal AD8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD8. Supported peripheral buses: General.
26AD9Digital_IOSignal terminal AD9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD9. Supported peripheral buses: General.
27AD10Digital_IOSignal terminal AD10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD10. Supported peripheral buses: General.
28AD11Digital_IOSignal terminal AD11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD11. Supported peripheral buses: General.
29AD12Digital_IOSignal terminal AD12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD12. Supported peripheral buses: General.
30AD13Digital_IOSignal terminal AD13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD13. Supported peripheral buses: General.
31AD14Digital_IOSignal terminal AD14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD14. Supported peripheral buses: General.
32PSPCFG0Digital_IOSignal terminal PSPCFG0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPCFG0. Supported peripheral buses: General.
33VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
34CSDigital_IOSignal terminal CS (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
35WRDigital_IOSignal terminal WR (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: WR. Supported peripheral buses: General.
36SIDigital_IOSignal terminal SI (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPISERIALDATAINPUT. Supported peripheral buses: SPI.
37SCKDigital_IOSignal terminal SCK (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPISERIALCLOCKINPUT. Supported peripheral buses: SPI.
38AD0Digital_IOSignal terminal AD0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
39AD1Digital_IOSignal terminal AD1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD1. Supported peripheral buses: General.
40AD2Digital_IOSignal terminal AD2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD2. Supported peripheral buses: General.
41AD3Digital_IOSignal terminal AD3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD3. Supported peripheral buses: General.
42VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
43VCAPDigital_IOSignal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
44VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
45A14/PSPCFG1Digital_IOSignal terminal A14/PSPCFG1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A14/PSPCFG1. Supported peripheral buses: General.
46VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
47VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
48WRH/B1SELDigital_IOSignal terminal WRH/B1SEL (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: WRH/B1SEL. Supported peripheral buses: General.
49CS#/CSDigital_IOSignal terminal CS#/CS (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: CS#/CS. Supported peripheral buses: General.
50SO/WR/WRL/EN/B0SELDigital_IOSignal terminal SO/WR/WRL/EN/B0SEL (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SO/WR/WRL/EN/B0SEL. Supported peripheral buses: General.
51SI/RD/RWDigital_IOSignal terminal SI/RD/RW (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SI/RD/RW. Supported peripheral buses: General.
52SCK/AL/PSPCFG4Digital_IOSignal terminal SCK/AL/PSPCFG4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SCK/AL/PSPCFG4. Supported peripheral buses: SPI.
53AD0Digital_IOSignal terminal AD0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
54AD1Digital_IOSignal terminal AD1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD1. Supported peripheral buses: General.
55AD2Digital_IOSignal terminal AD2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD2. Supported peripheral buses: General.
56AD3Digital_IOSignal terminal AD3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD3. Supported peripheral buses: General.
57A0Digital_IOSignal terminal A0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
58A1Digital_IOSignal terminal A1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
59A2Digital_IOSignal terminal A2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
60A3Digital_IOSignal terminal A3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
61A4Digital_IOSignal terminal A4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
62VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
63VCAPDigital_IOSignal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
64VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
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