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ATXMEGA256C3-AUR (TQFP-64(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATXMEGA256C3-AUR

MICROCHIPID: C219161TQFP-64(14x14) · 64 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATXMEGA256C3-AUR (TQFP-64(14x14))1IO12IO233V34NC5IO26IO37NC8PB29PB310CLK4X11–12PB613PB714GND15VCC16PC017PC118PC219PC320PC421PC522PC623PC724GND25VCC26PD027PD128PD229PD330PD431PD532PD664PA263PA162PA061AVCC60GND59PR158PR057#RESET/PDI56PDI55PF754PF653VCC52GND51PF550PF449PF348PF247PF146PF045VCC44GND43PE742PE641PE540PE439PE338PE237PE136PE035VCC34GND33PD7Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=14.00mm · Pitch e=0.80mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNCNo Connect (Leave Floating)
5IO2I/OGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7NCNCNo Connect (Leave Floating)
8PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
9PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
10CLK4XI/OMultiplexed I/O & Peripheral Pin CLK4X (General)
11–I/OMultiplexed I/O & Peripheral Pin – (General)
12PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
13PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
14GNDGNDGround Reference Pin (GND)
15VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
16PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
17PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
18PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
19PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
20PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
21PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
22PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
23PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
24GNDGNDGround Reference Pin (GND)
25VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
26PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
27PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
28PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
29PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
30PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
31PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
32PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
33PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
34GNDGNDGround Reference Pin (GND)
35VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
36PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
37PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
38PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
39PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
40PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
41PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
42PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
43PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
44GNDGNDGround Reference Pin (GND)
45VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
46PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
47PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
48PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
49PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
50PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
51PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
52GNDGNDGround Reference Pin (GND)
53VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
54PF6I/OMultiplexed I/O & Peripheral Pin PF6 (General)
55PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
56PDII/OMultiplexed I/O & Peripheral Pin PDI (General)
57#RESET/PDIISystem Enable & Hardware Reset (#RESET/PDI)
58PR0I/OMultiplexed I/O & Peripheral Pin PR0 (General)
59PR1I/OMultiplexed I/O & Peripheral Pin PR1 (General)
60GNDGNDGround Reference Pin (GND)
61AVCCPowerPower Supply Input (AVCC — 3.3V / 5.0V Standard Logic)
62PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
63PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
64PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATXMEGA256C3-AUR (MICROCHIP · TQFP-64(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 4. Package Dimensions (D×E×A)
TQFP-64(14x14) · 14.00×14.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATXMEGA256C3-AUR (TQFP-64(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for ATXMEGA256C3
P76 · p76_fig01444×362px
ATXMEGA256C3-AUR (TQFP-64(14x14)) — Figure 7-2. Crystal Oscillator Connection
Figure 7-2. Crystal Oscillator Connection
P76 · p76_fig02482×329px
ATXMEGA256C3-AUR (TQFP-64(14x14)) — Figure 7-3. External Clock Drive Configuration
Figure 7-3. External Clock Drive Configuration
P77 · p77_fig011998×484px
ATXMEGA256C3-AUR (TQFP-64(14x14)) — Figure 7-5. System Clock Selection and Prescalers
Figure 7-5. System Clock Selection and Prescalers
P77 · p77_fig01P77
ATXMEGA256C3-AUR (TQFP-64(14x14)) — Datasheet Page 77 (p77_fig01)
Datasheet Page 77 (p77_fig01)

Technical Specifications & Part Details (ATXMEGA256C3-AUR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATXMEGA256C3-AUR (TQFP-64(14x14)) is a 64-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-64(14x14))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-64(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.80mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-64(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATXMEGA256C3-AUR (TQFP-64(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATXMEGA256C3-AUR (TQFP-64(14x14))?

Manufactured by MICROCHIP, the ATXMEGA256C3-AUR is housed in a TQFP-64(14x14) package with 64 pins and a 0.80 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for ATXMEGA256C3-AUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATXMEGA256C3-AUR (TQFP-64(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.80 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATXMEGA256C3-AUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATXMEGA256C3-AUR (MICROCHIP, TQFP-64(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & ATXMEGA256C3 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4NCNo_ConnectNo Connect (Leave Floating)
5IO2Digital_IOGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7NCNo_ConnectNo Connect (Leave Floating)
8PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
9PB3Digital_IOSignal terminal PB3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
10CLK4XDigital_IOSignal terminal CLK4X (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK4X. Supported peripheral buses: General.
11–Digital_IOSignal terminal – (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: –. Supported peripheral buses: General.
12PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
13PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
17PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
18PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
19PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
20PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
21PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
22PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
23PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
25VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
26PD0Digital_IOSignal terminal PD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
27PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
28PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
29PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
30PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
31PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
32PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
33PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
34GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
35VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
36PE0Digital_IOSignal terminal PE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
37PE1Digital_IOSignal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
38PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
39PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
40PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
41PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
42PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
43PE7Digital_IOSignal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
44GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
45VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46PF0Digital_IOSignal terminal PF0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
47PF1Digital_IOSignal terminal PF1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
48PF2Digital_IOSignal terminal PF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
49PF3Digital_IOSignal terminal PF3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
50PF4Digital_IOSignal terminal PF4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
51PF5Digital_IOSignal terminal PF5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
52GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
53VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
54PF6Digital_IOSignal terminal PF6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General.
55PF7Digital_IOSignal terminal PF7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General.
56PDIDigital_IOSignal terminal PDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PDI. Supported peripheral buses: General.
57#RESET/PDIDigital_IOActive-low hardware reset terminal (#RESET/PDI): pulling this pin Low resets the processor core and peripherals.
58PR0Digital_IOSignal terminal PR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PR0. Supported peripheral buses: General.
59PR1Digital_IOSignal terminal PR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PR1. Supported peripheral buses: General.
60GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
61AVCCPower_InPrimary positive power supply input (AVCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
62PA0Digital_IOSignal terminal PA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
63PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
64PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
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