PIC16LF1579-I/P (PDIP-20) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC16LF1579-I/P (PDIP-20)?

Manufactured by MICROCHIP, the PIC16LF1579-I/P is housed in a PDIP-20 package with 20 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (VDD: Power Supply Input (VDD — 1.8V to 3.6V)), 2 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (/MCLR/VPP/RA3: Multiplexed I/O & Peripheral Pin /MCLR/VPP/RA3 (General)), 5 (RC5: Multiplexed I/O & Peripheral Pin RC5 (General)), 6 (RC4: Multiplexed I/O & Peripheral Pin RC4 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC16LF1579-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF1579-I/P (PDIP-20) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 2.54 mm, and 20 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF1579-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF1579-I/P (MICROCHIP, PDIP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 4.00mm × 4.00mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDD	Power	Power Supply Input (VDD — 1.8V to 3.6V)
2	RA5	I/O	Multiplexed I/O & Peripheral Pin RA5 (General)
3	RA4	I/O	Multiplexed I/O & Peripheral Pin RA4 (General)
4	/MCLR/VPP/RA3	I/O	Multiplexed I/O & Peripheral Pin /MCLR/VPP/RA3 (General)
5	RC5	I/O	Multiplexed I/O & Peripheral Pin RC5 (General)
6	RC4	I/O	Multiplexed I/O & Peripheral Pin RC4 (General)
7	RC3	I/O	Multiplexed I/O & Peripheral Pin RC3 (General)
8	RC6	I/O	Multiplexed I/O & Peripheral Pin RC6 (General)
9	RC7	I/O	Multiplexed I/O & Peripheral Pin RC7 (General)
10	RB7	I/O	Multiplexed I/O & Peripheral Pin RB7 (General)
11	RB6	I/O	Multiplexed I/O & Peripheral Pin RB6 (General)
12	RB5	I/O	Multiplexed I/O & Peripheral Pin RB5 (General)
13	RB4	I/O	Multiplexed I/O & Peripheral Pin RB4 (General)
14	RC2	I/O	Multiplexed I/O & Peripheral Pin RC2 (General)
15	RC1	I/O	Multiplexed I/O & Peripheral Pin RC1 (General)
16	RC0	I/O	Multiplexed I/O & Peripheral Pin RC0 (General)
17	RA2	I/O	Multiplexed I/O & Peripheral Pin RA2 (General)
18	RA1	I/O	Multiplexed I/O & Peripheral Pin RA1 (General)
19	RA0	I/O	Multiplexed I/O & Peripheral Pin RA0 (General)
20	VSS	GND	Ground Reference Pin (VSS)

PIN 1 VDD

Power

Power Supply Input (VDD — 1.8V to 3.6V)

Design note: Primary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC16LF1579-I/P (PDIP-20) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC16LF1579-I/P (PDIP-20) - 2. Standard Pinout (Top View)

True package pinout (20 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC16LF1579-I/P (PDIP-20) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC16LF1579-I/P (PDIP-20) - 4. Package Dimensions (D×E×A)

PDIP-20 · 4.00×4.00mm · Pitch 2.54mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC16LF1579-I/P (PDIP-20) - 5. Recommended Land Pattern

IPC-7351B Footprint (20 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC16LF1579-I/P (PDIP-20) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for PIC16LF1579

P1 · p01_fig01EXACT PACKAGE

14/20-Pin MCUs with High-Precision 16-Bit PWMs

P95 · p95_fig011777×1106px

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

P103 · p103_fig011777×1256px

FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

P259 · p259_fig011778×1123px

FIGURE 25-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

P259 · p259_fig021778×1225px

FIGURE 25-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

P259 · p259_fig02P259

Datasheet Page 259 (p259_fig02)

P316 · p316_fig011777×2580px

PIC16(L)F1574/5/8/9

P328 · p328_fig011778×2524px

PIC16(L)F1574/5/8/9

P336 · p336_fig011777×2521px

PIC16(L)F1574/5/8/9

P336 · p336_fig01P336

Datasheet Page 336 (p336_fig01)

P337 · p337_fig011778×2733px

PIC16LF1579-I/P (PDIP-20) —  2016 Microchip Technology Inc. DS40001782C-page 337 | PIC16(L)F1574/5/8/9 | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N

 2016 Microchip Technology Inc. DS40001782C-page 337 | PIC16(L)F1574/5/8/9 | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N

Technical Specifications & Part Details (PIC16LF1579-I/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC16LF1579-I/P (PDIP-20) is a 20-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 3.70 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V to 3.6V supply operation across -40°C to 85°C with integrated ADC, DAC, PWM interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to 85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

4.00 × 4.00 × 3.70 mm (A1=0.51 mm)

Package family: DIP (PDIP-20)

Pin Count & Lead PitchN / e

20 Pins | Pitch e = 2.54 mm (100.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

ADC, DAC, PWM

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol20 auto-grouped pins

IPC-7351B Land Pattern20 pads · Pitch 2.54mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-20)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

4.00 × 4.00 mm

Height (A) & Pitch (e)IPC-7351B

A=3.70mm · e=2.54mm

Pad Size (W × L)Level B

1.60 × 1.60 mm

Pins / Total PadsTopology

20P / 20Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PDIP-20	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF1579-I/P (PDIP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF1579-I/P (PDIP-20)?

Manufactured by MICROCHIP, the PIC16LF1579-I/P is housed in a PDIP-20 package with 20 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (VDD: Power Supply Input (VDD — 1.8V to 3.6V)), 2 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (/MCLR/VPP/RA3: Multiplexed I/O & Peripheral Pin /MCLR/VPP/RA3 (General)), 5 (RC5: Multiplexed I/O & Peripheral Pin RC5 (General)), 6 (RC4: Multiplexed I/O & Peripheral Pin RC4 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF1579-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF1579-I/P (PDIP-20) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 2.54 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF1579-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF1579-I/P (MICROCHIP, PDIP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & PIC16LF1579 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDD	Power_In	Primary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
2	RA5	Digital_IO	Signal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
3	RA4	Digital_IO	Signal terminal RA4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
4	/MCLR/VPP/RA3	Digital_IO	Signal terminal /MCLR/VPP/RA3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: /MCLR/VPP/RA3. Supported peripheral buses: General.
5	RC5	Digital_IO	Signal terminal RC5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
6	RC4	Digital_IO	Signal terminal RC4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
7	RC3	Digital_IO	Signal terminal RC3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
8	RC6	Digital_IO	Signal terminal RC6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
9	RC7	Digital_IO	Signal terminal RC7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
10	RB7	Digital_IO	Signal terminal RB7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB7. Supported peripheral buses: General.
11	RB6	Digital_IO	Signal terminal RB6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB6. Supported peripheral buses: General.
12	RB5	Digital_IO	Signal terminal RB5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
13	RB4	Digital_IO	Signal terminal RB4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
14	RC2	Digital_IO	Signal terminal RC2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
15	RC1	Digital_IO	Signal terminal RC1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
16	RC0	Digital_IO	Signal terminal RC0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
17	RA2	Digital_IO	Signal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
18	RA1	Digital_IO	Signal terminal RA1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
19	RA0	Digital_IO	Signal terminal RA0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
20	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.

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