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SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

SST39SF040-70-4I-NHE

MICROCHIPID: C219068PLCC-32(11.4x14) · 32 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SST39SF040-70-4I-NHE (PLCC-32(11.4x14))1A182A163A154A125A76A67A58A49A310A211A112A013DQ014DQ115DQ216VSS32VDD31WE#30A1729A1428A1327A826A925A1124OE#23A1022CE#21DQ720DQ619DQ518DQ417DQ3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
3231301234292827262524232221201918171615141312111098765E=11.40mm · Pitch e=1.27mmD=14.00mm-11-9-7-5-3-11357911121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 11.40mm × 14.00mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1A18I/OMultiplexed I/O & Peripheral Pin A18 (General)
2A16I/OMultiplexed I/O & Peripheral Pin A16 (General)
3A15I/OMultiplexed I/O & Peripheral Pin A15 (General)
4A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
5A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
6A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
7A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
8A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
9A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
10A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
11A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
12A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
13DQ0I/OMultiplexed I/O & Peripheral Pin DQ0 (General)
14DQ1I/OMultiplexed I/O & Peripheral Pin DQ1 (General)
15DQ2I/OMultiplexed I/O & Peripheral Pin DQ2 (General)
16VSSGNDGround Reference Pin (VSS)
17DQ3I/OMultiplexed I/O & Peripheral Pin DQ3 (General)
18DQ4I/OMultiplexed I/O & Peripheral Pin DQ4 (General)
19DQ5I/OMultiplexed I/O & Peripheral Pin DQ5 (General)
20DQ6I/OMultiplexed I/O & Peripheral Pin DQ6 (General)
21DQ7I/OMultiplexed I/O & Peripheral Pin DQ7 (General)
22CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
23A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
24OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
25A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
26A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
27A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
28A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
29A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
30A17I/OMultiplexed I/O & Peripheral Pin A17 (General)
31WE#I/OMultiplexed I/O & Peripheral Pin WE# (General)
32VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
PIN 1 A18
I/O
Multiplexed I/O & Peripheral Pin A18 (General)
Design note: Signal terminal A18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A18. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SST39SF040-70-4I-NHE (MICROCHIP · PLCC-32(11.4x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 2. Standard Pinout (Top View)
True package pinout (32 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 4. Package Dimensions (D×E×A)
PLCC-32(11.4x14) · 11.40×14.00mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (32 Pads)Expand ›
6. Application SchematicSCHEMATIC
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for SST39SF040
P5 · p05_fig03EXACT PACKAGE
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Figure 4: Pin Assignments for 32-pin PDIP
Figure 4: Pin Assignments for 32-pin PDIP
P1 · p01_fig012210×401px
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Data Sheet | 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
Data Sheet | 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040
P2 · p02_fig012210×349px
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 | Data Sheet Product Description
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 | Data Sheet Product Description
P5 · p05_fig012210×401px
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — SST39SF010A
SST39SF010A
P5 · p05_fig021712×799px
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
P5 · p05_fig03P5
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Datasheet Page 5 (p05_fig03)
Datasheet Page 5 (p05_fig03)
P26 · p26_fig012210×1825px
SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) — Figure 21:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
Figure 21:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

Technical Specifications & Part Details (SST39SF040-70-4I-NHE)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) is a 32-pin standard electronic & interconnect component featuring a 14.00 × 11.40 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
14 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 11.40 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-32(11.4x14))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol32 auto-grouped pins
OK
IPC-7351B Land Pattern32 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PLCC-32(11.4x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 11.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.62 × 2.40 mm
Pins / Total PadsTopology
32P / 32Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-32(11.4x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SST39SF040-70-4I-NHE (PLCC-32(11.4x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SST39SF040-70-4I-NHE (PLCC-32(11.4x14))?

Manufactured by MICROCHIP, the SST39SF040-70-4I-NHE is housed in a PLCC-32(11.4x14) package with 32 pins and a 1.27 mm lead pitch. Key pins include: 1 (A18: Multiplexed I/O & Peripheral Pin A18 (General)), 2 (A16: Multiplexed I/O & Peripheral Pin A16 (General)), 3 (A15: Multiplexed I/O & Peripheral Pin A15 (General)), 4 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 5 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 6 (A6: Multiplexed I/O & Peripheral Pin A6 (General)).

What are the IPC-7351B PCB Footprint dimensions for SST39SF040-70-4I-NHE?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SST39SF040-70-4I-NHE (PLCC-32(11.4x14)) has a nominal body envelope of 11.40 × 14.00 mm, pitch e = 1.27 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SST39SF040-70-4I-NHE?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SST39SF040-70-4I-NHE (MICROCHIP, PLCC-32(11.4x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & SST39SF040 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1A18Digital_IOSignal terminal A18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A18. Supported peripheral buses: General.
2A16Digital_IOSignal terminal A16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A16. Supported peripheral buses: General.
3A15Digital_IOSignal terminal A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A15. Supported peripheral buses: General.
4A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
5A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
6A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
7A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
8A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
9A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
10A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
11A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
12A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
13DQ0Digital_IOSignal terminal DQ0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ0. Supported peripheral buses: General.
14DQ1Digital_IOSignal terminal DQ1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ1. Supported peripheral buses: General.
15DQ2Digital_IOSignal terminal DQ2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ2. Supported peripheral buses: General.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17DQ3Digital_IOSignal terminal DQ3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ3. Supported peripheral buses: General.
18DQ4Digital_IOSignal terminal DQ4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ4. Supported peripheral buses: General.
19DQ5Digital_IOSignal terminal DQ5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ5. Supported peripheral buses: General.
20DQ6Digital_IOSignal terminal DQ6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ6. Supported peripheral buses: General.
21DQ7Digital_IOSignal terminal DQ7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ7. Supported peripheral buses: General.
22CE#Digital_IOSignal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
23A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
24OE#Digital_IOSignal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
25A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
26A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
27A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
28A13Digital_IOSignal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
29A14Digital_IOSignal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
30A17Digital_IOSignal terminal A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A17. Supported peripheral buses: General.
31WE#Digital_IOSignal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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