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PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC24F16KA102-I/ML

MICROCHIPID: C219063QFN-28-EP(6x6) · 29 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC24F16KA102-I/ML (QFN-28-EP(6x6))1ST2ST3ST4ST5ST6ANA7ST8—9ST10—11ST12ST13—14ST15ST29EP28AN1/VREF-/CN27AN0/VREF+/CN26#MCLR/VPP/RA25VDD24VSS23IO1222IO1121IO1020ANA19ANA18—17—16—Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.65mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1STI/OMultiplexed I/O & Peripheral Pin ST (General)
2STI/OMultiplexed I/O & Peripheral Pin ST (General)
3STI/OMultiplexed I/O & Peripheral Pin ST (General)
4STI/OMultiplexed I/O & Peripheral Pin ST (General)
5STI/OMultiplexed I/O & Peripheral Pin ST (General)
6ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
7STI/OMultiplexed I/O & Peripheral Pin ST (General)
8—I/OMultiplexed I/O & Peripheral Pin — (General)
9STI/OMultiplexed I/O & Peripheral Pin ST (General)
10—I/OMultiplexed I/O & Peripheral Pin — (General)
11STI/OMultiplexed I/O & Peripheral Pin ST (General)
12STI/OMultiplexed I/O & Peripheral Pin ST (SPI)
13—I/OMultiplexed I/O & Peripheral Pin — (General)
14STI/OMultiplexed I/O & Peripheral Pin ST (General)
15STI/OMultiplexed I/O & Peripheral Pin ST (General)
16—I/OMultiplexed I/O & Peripheral Pin — (General)
17—I/OMultiplexed I/O & Peripheral Pin — (General)
18—I/OMultiplexed I/O & Peripheral Pin — (General)
19ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
20ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
21IO10I/OGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11I/OGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12I/OGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24VSSGNDGround Reference Pin (VSS)
25VDDPowerPower Supply Input (VDD — 1.8V to 3.6V)
26#MCLR/VPP/RA5I/OMultiplexed I/O & Peripheral Pin #MCLR/VPP/RA5 (General)
27AN0/VREF+/CN2/RA0AnalogMultiplexed I/O & Peripheral Pin AN0/VREF+/CN2/RA0 (General)
28AN1/VREF-/CN3/RA1AnalogMultiplexed I/O & Peripheral Pin AN1/VREF-/CN3/RA1 (General)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 ST
I/O
Multiplexed I/O & Peripheral Pin ST (General)
Design note: RB0
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC24F16KA102-I/ML (MICROCHIP · QFN-28-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for PIC24F16KA10
P1 · p01_fig01752×399px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — PIC24F16KA102 Family
PIC24F16KA102 Family
P1 · p01_fig01P1
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011777×1640px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — DS39927C-page 2  2008-2011 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technolog
DS39927C-page 2  2008-2011 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technolog
P2 · p02_fig02765×211px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — ISBN: 978-1-61341-690-7
ISBN: 978-1-61341-690-7
P12 · p12_fig011541×2030px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM
FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM
P18 · p18_fig01867×940px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
P21 · p21_fig01867×1876px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
P189 · p189_fig011777×1039px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT
P189 · p189_fig01P189
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — Datasheet Page 189 (p189_fig01)
Datasheet Page 189 (p189_fig01)
P190 · p190_fig01951×658px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT
FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT
P190 · p190_fig021777×832px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION
P251 · p251_fig011777×2309px
PIC24F16KA102-I/ML (QFN-28-EP(6x6)) — 30.1 Package Marking Information
30.1 Package Marking Information

Technical Specifications & Part Details (PIC24F16KA102-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC24F16KA102-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24F16KA102-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24F16KA102-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC24F16KA102-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 2 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 3 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 4 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 5 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 6 (ANA: Multiplexed I/O & Peripheral Pin ANA (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24F16KA102-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24F16KA102-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24F16KA102-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24F16KA102-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC24F16KA10 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
2STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
3STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
4STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
5STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
6ANADigital_IOSignal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
7STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
8—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
9STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1CTS. Supported peripheral buses: General.
10—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General.
11STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
12STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: SPI.
13—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
14STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
15STDigital_IOSignal terminal ST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
16—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
17—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
18—Digital_IOSignal terminal — (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
19ANADigital_IOSignal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
20ANADigital_IOSignal terminal ANA (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
21IO10Digital_IOGPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0
22IO11Digital_IOGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23IO12Digital_IOGPIO12 / RTC_GPIO12 / TOUCH12 / ADC2_CH1 / FSPICLK
24VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
25VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
26#MCLR/VPP/RA5Digital_IOSignal terminal #MCLR/VPP/RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: #MCLR/VPP/RA5. Supported peripheral buses: General.
27AN0/VREF+/CN2/RA0AnalogSignal terminal AN0/VREF+/CN2/RA0 (Analog, 1.8V to 3.6V domain). Multiplexed alternate functions: AN0/VREF+/CN2/RA0. Supported peripheral buses: General.
28AN1/VREF-/CN3/RA1AnalogSignal terminal AN1/VREF-/CN3/RA1 (Analog, 1.8V to 3.6V domain). Multiplexed alternate functions: AN1/VREF-/CN3/RA1. Supported peripheral buses: General.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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