ESP32-U4WDH (QFN-48-EP(5x5)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 5.00mm × 5.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
2	LNA_IN	I/O	Multiplexed I/O & Peripheral Pin LNA_IN (General)
3	VDD3P3	Power	Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
4	VDD3P3	Power	Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))
5	SENSOR_VP	I	Input-Only Pin SENSOR_VP (ADC)
6	SENSOR_CAPP	I/O	Multiplexed I/O & Peripheral Pin SENSOR_CAPP (General)
7	SENSOR_CAPN	I/O	Multiplexed I/O & Peripheral Pin SENSOR_CAPN (General)
8	SENSOR_VN	I	Input-Only Pin SENSOR_VN (ADC)
9	CHIP_PU	I	System Enable & Hardware Reset (CHIP_PU)
10	VDET_1	I/O	Multiplexed I/O & Peripheral Pin VDET_1 (General)
11	VDET_2	I/O	Multiplexed I/O & Peripheral Pin VDET_2 (General)
12	32K_XP	I/O	Multiplexed I/O & Peripheral Pin 32K_XP (General)
13	32K_XN	I/O	Multiplexed I/O & Peripheral Pin 32K_XN (General)
14	GPIO25	I/O	Multiplexed I/O & Peripheral Pin GPIO25 (General)
15	GPIO26	I/O	Multiplexed I/O & Peripheral Pin GPIO26 (General)
16	GPIO27	I/O	Multiplexed I/O & Peripheral Pin GPIO27 (General)
17	MTMS	I/O	Multiplexed I/O & Peripheral Pin MTMS (SWD/JTAG)
18	MTDI	I/O	Multiplexed I/O & Peripheral Pin MTDI (SWD/JTAG)
19	VDD3P3_RTC	Power	Power Supply Input (VDD3P3_RTC — 3.3V VDD3P3 (3.0V ~ 3.6V))
20	MTCK	I/O	Multiplexed I/O & Peripheral Pin MTCK (SWD/JTAG)
21	MTDO	I/O	Multiplexed I/O & Peripheral Pin MTDO (SWD/JTAG)
22	GPIO2	I/O	Multiplexed I/O & Peripheral Pin GPIO2 (General)
23	GPIO0	I/O	Multiplexed I/O & Peripheral Pin GPIO0 (General)
24	GPIO4	I/O	Multiplexed I/O & Peripheral Pin GPIO4 (General)
25	GPIO16	I/O	Multiplexed I/O & Peripheral Pin GPIO16 (General)
26	VDD_SDIO	Power	Power Supply Input (VDD_SDIO — 3.3V VDD3P3 (3.0V ~ 3.6V))
27	GPIO17	I/O	Multiplexed I/O & Peripheral Pin GPIO17 (General)
28	SD_DATA_2	I/O	Multiplexed I/O & Peripheral Pin SD_DATA_2 (General)
29	SD_DATA_3	I/O	Multiplexed I/O & Peripheral Pin SD_DATA_3 (General)
30	SD_CMD	I/O	Multiplexed I/O & Peripheral Pin SD_CMD (General)
31	SD_CLK	I/O	Multiplexed I/O & Peripheral Pin SD_CLK (General)
32	SD_DATA_0	I/O	Multiplexed I/O & Peripheral Pin SD_DATA_0 (General)
33	SD_DATA_1	I/O	Multiplexed I/O & Peripheral Pin SD_DATA_1 (General)
34	GPIO5	I/O	Multiplexed I/O & Peripheral Pin GPIO5 (General)
35	GPIO18	I/O	Multiplexed I/O & Peripheral Pin GPIO18 (General)
36	GPIO23	I/O	Multiplexed I/O & Peripheral Pin GPIO23 (General)
37	VDD3P3_CPU	Power	Power Supply Input (VDD3P3_CPU — 3.3V VDD3P3 (3.0V ~ 3.6V))
38	GPIO19	I/O	Multiplexed I/O & Peripheral Pin GPIO19 (General)
39	GPIO22	I/O	Multiplexed I/O & Peripheral Pin GPIO22 (General)
40	U0RXD	I/O	Multiplexed I/O & Peripheral Pin U0RXD (UART)
41	U0TXD	I/O	Multiplexed I/O & Peripheral Pin U0TXD (UART)
42	GPIO21	I/O	Multiplexed I/O & Peripheral Pin GPIO21 (General)
43	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
44	XTAL_N	I/O	Multiplexed I/O & Peripheral Pin XTAL_N (RTC/CLK)
45	XTAL_P	I/O	Multiplexed I/O & Peripheral Pin XTAL_P (RTC/CLK)
46	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))
47	CAP2	I/O	Multiplexed I/O & Peripheral Pin CAP2 (General)
48	CAP1	I/O	Multiplexed I/O & Peripheral Pin CAP1 (General)
49	GND	GND	Exposed Thermal & Ground Pad (GND)

PIN 1 VDDA

Power

Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))

Design note: Primary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ESP32-U4WDH (QFN-48-EP(5x5)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ESP32-U4WDH (QFN-48-EP(5x5)) - 2. Standard Pinout (Top View)

True package pinout (49 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ESP32-U4WDH (QFN-48-EP(5x5)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ESP32-U4WDH (QFN-48-EP(5x5)) - 4. Package Dimensions (D×E×A)

QFN-48-EP(5x5) · 5.00×5.00mm · Pitch 0.35mmExpand ›

5. Recommended Land PatternLAND PATTERN

ESP32-U4WDH (QFN-48-EP(5x5)) - 5. Recommended Land Pattern

IPC-7351B Footprint (49 Pads)Expand ›

6. Application SchematicSCHEMATIC

ESP32-U4WDH (QFN-48-EP(5x5)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for ESP32-U4WDH

P51 · p51_fig01EXACT PACKAGE

2.1 管脚布局。

P51 · p51_fig02EXACT PACKAGE

图5-2. QFN48 (5x5 mm) 封装

P51 · p51_fig03EXACT PACKAGE

图5-2. QFN48 (5x5 mm) 封装

P51 · p51_fig04EXACT PACKAGE

图5-1. QFN48 (6x6 mm) 封装

P1 · p01_fig01646×314px

www.espressif.com

P2 · p02_fig011709×1747px

v3.0 或v3.1。

P2 · p02_fig021037×1283px

ESP32 功能框图

P12 · p12_fig011639×1471px

图2-1. ESP32 管脚布局（封装为QFN 6*6，顶视图）

P13 · p13_fig011669×1468px

图2-2. ESP32 管脚布局（封装为QFN 5*5，顶视图）

P19 · p19_fig011530×514px

图2-4. 上电和复位时序参数图

Technical Specifications & Part Details (ESP32-U4WDH)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Wireless Wi-Fi / Bluetooth LE SoC Module

Detailed Overview:ESP32-U4WDH (QFN-48-EP(5x5)) is a 48-pin wireless wi-fi / bluetooth le soc module featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 65 V ~ 2.0 V supply operation across 40 °C ~ 105 °C with integrated Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG interfaces.

Operating Supply VoltageV_CC / V_DD

65 V ~ 2.0 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40 °C ~ 105 °C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

2.4 GHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_TX(peak) ≈ 310 mA @ 3.3V | Deep-Sleep ≈ 10 µA | I_GPIO(max) = 40 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

5.00 × 5.00 × 0.85 mm (A1=0.03 mm)

Package family: QFN (QFN-48-EP(5x5))

Pin Count & Lead PitchN / e

48 Pins | Pitch e = 0.35 mm (13.8 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Wi-Fi, Bluetooth / BLE, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, RTC/CLK, SWD/JTAG

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (MTDI, MTDO, GPIO0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol49 auto-grouped pins

IPC-7351B Land Pattern49 pads · Pitch 0.35mm

IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — ESP32-U4WDH (2)

Select package variant or sibling MPN sharing this datasheet

QFN-48-EP(5x5) · 49P

ESP32-U4WDH

ESPRESSIF·QFN-48-EP(5x5)

IPC-7351B

49P5.0×5.0×0.85mmP=0.35mm

ESP32-U4WDH (QFN-48-EP(5x5))

QFN-48-EP(5x5) · 49P

ESP32-U4WDH

ESPRESSIF·QFN-48-EP(5x5)

IPC-7351B

49P5.0×5.0×0.85mmP=0.35mm

ESP32-U4WDH (QFN-48-EP(5x5))

Mechanical Dimensions & Land Pattern (QFN-48-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

5.00 × 5.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.35mm

Pad Size (W × L)Level B

0.16 × 0.58 mm

Pins / Total PadsTopology

49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
C1, C2 BOM	22µF (or 10µF) X5R + 100nF X7R 0805 + 0402	3V3 supply decoupling for ~500mA Wi-Fi TX bursts — place closest to 3V3 pin; supply must deliver >= 600mA.
R_en + C_en BOM	R = 10kΩ to 3V3 + C = 1µF to GND 0402 / 0603	Power-On Reset RC delay at EN (CHIP_PU) — 1µF capacitor at EN is REQUIRED for reliable cold boot.
R_boot + SW1 BOM	10kΩ Pull-up + BOOT button 0402 + SMD	Firmware boot-mode strap (IO0 on ESP32/S2/S3, IO9 on ESP32-C3) — on C3 pull IO8 high via 10kΩ for UART/USB download.
D_esd BOM	USBLC6-2SC6 / LESD5D5.0CT1G SOT-23-6 / SOD-523	ESD surge protection on USB D+/D- — place right next to USB Type-C connector before IO18/IO19/IO20.
ESP32-S3-MINI-1-N8 / 1U-N4R2 Espressif	100% Drop-in	Same 15.4×15.4mm 65-pad footprint as ESP32-S2-MINI-2 — verify USB GPIO 19/20 pin mapping.

Technical Frequently Asked Questions (FAQ) — ESP32-U4WDH (QFN-48-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ESP32-U4WDH (QFN-48-EP(5x5))?

Manufactured by ESPRESSIF, the ESP32-U4WDH is housed in a QFN-48-EP(5x5) package with 49 pins and a 0.35 mm lead pitch, supporting a VCC supply range of 65 V ~ 2.0 V. Key pins include: 1 (VDDA: Power Supply Input (VDDA — 3.3V VDD3P3 (3.0V ~ 3.6V))), 2 (LNA_IN: Multiplexed I/O & Peripheral Pin LNA_IN (General)), 3 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 4 (VDD3P3: Power Supply Input (VDD3P3 — 3.3V VDD3P3 (3.0V ~ 3.6V))), 5 (SENSOR_VP: Input-Only Pin SENSOR_VP (ADC)), 6 (SENSOR_CAPP: Multiplexed I/O & Peripheral Pin SENSOR_CAPP (General)).

What are the IPC-7351B PCB Footprint dimensions for ESP32-U4WDH?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ESP32-U4WDH (QFN-48-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.35 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ESP32-U4WDH?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ESP32-U4WDH (ESPRESSIF, QFN-48-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & ESP32-U4WDH Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
2	LNA_IN	RF_50Ohm	Signal terminal LNA_IN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: LNA_IN. Supported peripheral buses: General.
3	VDD3P3	Power_In	Primary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
4	VDD3P3	Power_In	Primary positive power supply input (VDD3P3) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
5	SENSOR_VP	Digital_IO	Signal terminal SENSOR_VP (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SENSOR_VP. Supported peripheral buses: ADC.
6	SENSOR_CAPP	Digital_IO	Signal terminal SENSOR_CAPP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SENSOR_CAPP. Supported peripheral buses: General.
7	SENSOR_CAPN	Digital_IO	Signal terminal SENSOR_CAPN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SENSOR_CAPN. Supported peripheral buses: General.
8	SENSOR_VN	Digital_IO	Signal terminal SENSOR_VN (I, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SENSOR_VN. Supported peripheral buses: ADC.
9	CHIP_PU	Digital_IO	Chip enable and power-on reset control input (CHIP_PU): High enables the SoC; Low powers down the chip into reset.
10	VDET_1	Digital_IO	Signal terminal VDET_1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: VDET_1. Supported peripheral buses: General.
11	VDET_2	Digital_IO	Signal terminal VDET_2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: VDET_2. Supported peripheral buses: General.
12	32K_XP	Digital_IO	Signal terminal 32K_XP (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: 32K_XP. Supported peripheral buses: General.
13	32K_XN	Digital_IO	Signal terminal 32K_XN (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: 32K_XN. Supported peripheral buses: General.
14	GPIO25	Digital_IO	Signal terminal GPIO25 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO25. Supported peripheral buses: General.
15	GPIO26	Digital_IO	Signal terminal GPIO26 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO26. Supported peripheral buses: General.
16	GPIO27	Digital_IO	Signal terminal GPIO27 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO27. Supported peripheral buses: General.
17	MTMS	Digital_IO	Signal terminal MTMS (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTMS. Supported peripheral buses: SWD/JTAG.
18	MTDI	Digital_IO	Signal terminal MTDI (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDI. Supported peripheral buses: SWD/JTAG.
19	VDD3P3_RTC	Power_In	Primary positive power supply input (VDD3P3_RTC) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
20	MTCK	Digital_IO	Signal terminal MTCK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTCK. Supported peripheral buses: SWD/JTAG.
21	MTDO	Digital_IO	Signal terminal MTDO (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: MTDO. Supported peripheral buses: SWD/JTAG.
22	GPIO2	Digital_IO	Signal terminal GPIO2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO2. Supported peripheral buses: General.
23	GPIO0	Digital_IO	Signal terminal GPIO0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO0. Supported peripheral buses: General.
24	GPIO4	Digital_IO	Signal terminal GPIO4 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO4. Supported peripheral buses: General.
25	GPIO16	Digital_IO	Signal terminal GPIO16 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO16. Supported peripheral buses: General.
26	VDD_SDIO	Power_In	Primary positive power supply input (VDD_SDIO) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
27	GPIO17	Digital_IO	Signal terminal GPIO17 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO17. Supported peripheral buses: General.
28	SD_DATA_2	Digital_IO	Signal terminal SD_DATA_2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_DATA_2. Supported peripheral buses: General.
29	SD_DATA_3	Digital_IO	Signal terminal SD_DATA_3 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_DATA_3. Supported peripheral buses: General.
30	SD_CMD	Digital_IO	Signal terminal SD_CMD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_CMD. Supported peripheral buses: General.
31	SD_CLK	Digital_IO	Signal terminal SD_CLK (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_CLK. Supported peripheral buses: General.
32	SD_DATA_0	Digital_IO	Signal terminal SD_DATA_0 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_DATA_0. Supported peripheral buses: General.
33	SD_DATA_1	Digital_IO	Signal terminal SD_DATA_1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: SD_DATA_1. Supported peripheral buses: General.
34	GPIO5	Digital_IO	Signal terminal GPIO5 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
35	GPIO18	Digital_IO	Signal terminal GPIO18 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO18. Supported peripheral buses: General.
36	GPIO23	Digital_IO	Signal terminal GPIO23 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO23. Supported peripheral buses: General.
37	VDD3P3_CPU	Power_In	Primary positive power supply input (VDD3P3_CPU) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
38	GPIO19	Digital_IO	Signal terminal GPIO19 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO19. Supported peripheral buses: General.
39	GPIO22	Digital_IO	Signal terminal GPIO22 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO22. Supported peripheral buses: General.
40	U0RXD	Digital_IO	Signal terminal U0RXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0RXD. Supported peripheral buses: UART.
41	U0TXD	Digital_IO	Signal terminal U0TXD (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: U0TXD. Supported peripheral buses: UART.
42	GPIO21	Digital_IO	Signal terminal GPIO21 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: GPIO21. Supported peripheral buses: General.
43	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
44	XTAL_N	Digital_IO	Signal terminal XTAL_N (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_N. Supported peripheral buses: RTC/CLK.
45	XTAL_P	Digital_IO	Signal terminal XTAL_P (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: XTAL_P. Supported peripheral buses: RTC/CLK.
46	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD3P3 (3.0V ~ 3.6V) domain (Max rating: 3.6V).
47	CAP2	Digital_IO	Signal terminal CAP2 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: CAP2. Supported peripheral buses: General.
48	CAP1	Digital_IO	Signal terminal CAP1 (I/O, 3.3V VDD3P3 (3.0V ~ 3.6V) domain). Multiplexed alternate functions: CAP1. Supported peripheral buses: General.
49	GND	GND	Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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