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STM32L072KBU7TR (UFQFPN-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L072KBU7TR

STID: C2057219UFQFPN-32(5x5) · 33 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L072KBU7TR (UFQFPN-32(5x5))1PC14 - OSC322IO23NRST4VSSA5VDDA6PA07PA18PA29PA310PA411PA512PA613PA714PB015PB116VSS17VDD33VSS32VDD31VSS30BOOT029PB728PB627PB526PB425PA1424VDD_USB23PA1322PA1221PA1120PA1019PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
2IO2I/OGeneral Purpose Digital I/O Pin IO2
3NRSTISystem Enable & Hardware Reset (NRST)
4VSSAGNDGround Reference Pin (VSSA)
5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
14PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
15PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (USB, UART, I2C, RTC/CLK)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C)
21PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
22PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
23PA13I/OMultiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)
24VDD_USBPowerPower Supply Input (VDD_USB — 3.3V VDD (Max 4.0V))
25PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG)
26PB4I/OMultiplexed I/O & Peripheral Pin PB4 (UART, SPI, I2C, PWM)
27PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
28PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
29PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
30BOOT0IInput-Only Pin BOOT0 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
33VSSGNDGround Reference Pin (VSS)
PIN 1 PC14 - OSC32_IN (PC14)
I/O
Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
Design note: Add: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L072KBU7TR (ST · UFQFPN-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L072KBU7TR (UFQFPN-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L072KBU7TR (UFQFPN-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L072KBU7TR (UFQFPN-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L072KBU7TR (UFQFPN-32(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L072KBU7TR (UFQFPN-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L072KBU7TR (UFQFPN-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32L072
P43 · p43_fig01EXACT PACKAGE
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 11. STM32L072xx UFQFPN32 pinout
Figure 11. STM32L072xx UFQFPN32 pinout
P148 · p148_fig01EXACT PACKAGE
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 66. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint
Figure 66. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint
P150 · p150_fig01EXACT PACKAGE
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 68. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
Figure 68. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
P151 · p151_fig01EXACT PACKAGE
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 69. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
Figure 69. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
P37 · p37_fig011546×1379px
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 3. STM32L072xx LQFP100 pinout
Figure 3. STM32L072xx LQFP100 pinout
P43 · p43_fig01P43
STM32L072KBU7TR (UFQFPN-32(5x5)) — Datasheet Page 43 (p43_fig01)
Datasheet Page 43 (p43_fig01)
P61 · p61_fig011751×1623px
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P61 · p61_fig021875×770px
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 15. Current consumption measurement scheme
Figure 15. Current consumption measurement scheme
P61 · p61_fig01P61
STM32L072KBU7TR (UFQFPN-32(5x5)) — Datasheet Page 61 (p61_fig01)
Datasheet Page 61 (p61_fig01)
P105 · p105_fig011546×705px
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 31. Typical connection diagram using the ADC
Figure 31. Typical connection diagram using the ADC
P105 · p105_fig021546×975px
STM32L072KBU7TR (UFQFPN-32(5x5)) — Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
P151 · p151_fig01P151
STM32L072KBU7TR (UFQFPN-32(5x5)) — Datasheet Page 151 (p151_fig01)
Datasheet Page 151 (p151_fig01)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32L072KBU7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L072KBU7TR (UFQFPN-32(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
19 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.55 mm (A1=0.05 mm)
Package family: QFN (UFQFPN-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.75 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L072KBU7TR (UFQFPN-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L072KBU7TR (UFQFPN-32(5x5))?

Manufactured by ST, the STM32L072KBU7TR is housed in a UFQFPN-32(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (NRST: System Enable & Hardware Reset (NRST)), 4 (VSSA: Ground Reference Pin (VSSA)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L072KBU7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L072KBU7TR (UFQFPN-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L072KBU7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L072KBU7TR (ST, UFQFPN-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32L072 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
3NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
4VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
14PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
15PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: USB, UART, I2C, RTC/CLK.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL, I2C3_SMBA. Supported peripheral buses: UART, I2C, RTC/CLK.
20PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
21PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI.
22PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI.
23PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB, SWD/JTAG.
24VDD_USBPower_InPrimary positive power supply input (VDD_USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG.
26PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, I2C3_SDA. Supported peripheral buses: UART, SPI, I2C, PWM.
27PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: UART, SPI, I2C.
28PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
29PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
30BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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