ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32F103ZGH6JTR (BGA-144) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103ZGH6JTR

STBGA-144 · 144 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103ZGH6JTR (BGA-144)A1PC13TAMPER -A2PE3A3PE2A4PE1A5PE0A6PB4A7PB3A8PD6A9PD7A10PA15A11PA14A12PA13B1PC14OSC32 INB2PE4B3PE5B4PE6B5PB9B6PB5B7PG15B8PG12B9PD5B10PC11B11PC10B12PA12C1PC15 - OSC32C2VBATC3PF0C4PF1C5PB8C6PB6C7PG14C8PG11C9PD4C10PC12C11NotconnectedC12PA11D1OSC_IND2VSS_5D3VDD_5D4PF2D5BOOT0D6PB7D7PG13D8PG10D9PD3D10PD1D11PA10D12PA9E1OSC_OUTE2PF3E3PF4E4PF5E5VSS_3E6VSS_11E7VSS_10E8PG9E9PD2E10PD0E11PC9E12PA8F1NRSTF2PF7F3PF6F4VDD_4F5VDD_3F6VDD_11F7VDD_10F8VDD_8F9VDD_2F10VDD_9F11PC8F12PC7M12PB13M11PB12M10PB11M9PB10M8PE15M7PE7M6PF14M5PF11M4PB1M3PA7M2PA3M1VDDAL12PB15L11PB14L10PD12L9PD8L8PE14L7PE8L6PF15L5PF12L4PB0L3PA6L2PA2L1VREF+K12PD15K11PD14K10PD13K9PD9K8PE13K7PE9K6PG0K5PF13K4PC5K3PA5K2PA1K1VREF-J12PG2J11PG3J10PG4J9PD10J8PE12J7PE10J6PG1J5PB2J4PC4J3PA4J2PA0WKUP -J1VSSAH12PG5H11PG6H10PG7H9PD11H8PE11H7VSS_1H6VSS_7H5VSS_6H4PC3H3PC2H2PC1H1PC0G12PC6G11PG8G10VSS_9G9VSS_2G8VSS_8G7VDD_1G6VDD_7G5VDD_6G4VSS_4G3PF8G2PF9G1PF10Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C6C7C8C9C10C11C12D1D2D3D4D5D6D7D8D9D10D11D12E1E2E3E4E5E6E7E8E9E10E11E12F1F2F3F4F5F6F7F8F9F10F11F12G1G2G3G4G5G6G7G8G9G10G11G12H1H2H3H4H5H6H7H8H9H10H11H12J1J2J3J4J5J6J7J8J9J10J11J12K1K2K3K4K5K6K7K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=10.00mm · Pitch e=0.80mmD=10.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
A2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A5PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
A6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
A7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
A8PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A9PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A10PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
A11PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A12PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
B1PC14OSC32 IN(5) -_I/OMultiplexed I/O & Peripheral Pin PC14OSC32 IN(5) -_ (RTC/CLK)
B2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
B4PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
B5PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
B6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
B7PG15I/OMultiplexed I/O & Peripheral Pin PG15 (General)
B8PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
B9PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
B12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
C1PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
C2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
C4PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
C5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
C6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
C7PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
C8PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
C9PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
C10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
C11NotconnectedI/OMultiplexed I/O & Peripheral Pin Notconnected (General)
C12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
D1OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
D2VSS_5GNDGround Reference Pin (VSS_5)
D3VDD_5PowerPower Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
D4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
D5BOOT0IInput-Only Pin BOOT0 (General)
D6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
D7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
D8PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
D9PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
D10PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D12PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
E1OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
E2PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
E3PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
E4PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
E5VSS_3GNDGround Reference Pin (VSS_3)
E6VSS_11GNDGround Reference Pin (VSS_11)
E7VSS_10GNDGround Reference Pin (VSS_10)
E8PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
E9PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
E10PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
E11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
F1NRSTISystem Enable & Hardware Reset (NRST)
F2PF7I/OMultiplexed I/O & Peripheral Pin PF7 (ADC)
F3PF6I/OMultiplexed I/O & Peripheral Pin PF6 (ADC)
F4VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
F5VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
F6VDD_11PowerPower Supply Input (VDD_11 — 3.3V VDD (Max 4.0V))
F7VDD_10PowerPower Supply Input (VDD_10 — 3.3V VDD (Max 4.0V))
F8VDD_8PowerPower Supply Input (VDD_8 — 3.3V VDD (Max 4.0V))
F9VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
F10VDD_9PowerPower Supply Input (VDD_9 — 3.3V VDD (Max 4.0V))
F11PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
G1PF10I/OMultiplexed I/O & Peripheral Pin PF10 (ADC)
G2PF9I/OMultiplexed I/O & Peripheral Pin PF9 (ADC)
G3PF8I/OMultiplexed I/O & Peripheral Pin PF8 (ADC)
G4VSS_4GNDGround Reference Pin (VSS_4)
G5VDD_6PowerPower Supply Input (VDD_6 — 3.3V VDD (Max 4.0V))
G6VDD_7PowerPower Supply Input (VDD_7 — 3.3V VDD (Max 4.0V))
G7VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
G8VSS_8GNDGround Reference Pin (VSS_8)
G9VSS_2GNDGround Reference Pin (VSS_2)
G10VSS_9GNDGround Reference Pin (VSS_9)
G11PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
G12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
H3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
H4PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
H5VSS_6GNDGround Reference Pin (VSS_6)
H6VSS_7GNDGround Reference Pin (VSS_7)
H7VSS_1GNDGround Reference Pin (VSS_1)
H8PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
H9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
H10PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
H11PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
H12PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
J1VSSAGNDGround Reference Pin (VSSA)
J2PA0WKUP -I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC)
J3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
J5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
J6PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
J7PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
J8PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
J9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
J10PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
J11PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
J12PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
K1VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
K2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
K3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
K4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
K5PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
K6PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
K7PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K8PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
K9PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
K10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
K11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
K12PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
L3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
L4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
L5PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
L6PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
L8PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
L9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
L10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
L11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
L12PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
M3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
M4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
M5PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
M6PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
M9PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
M10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
M11PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
M12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI)
PIN A1 PC13TAMPER - - RTC
I/O
Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
Design note: PC13(6) | Alt: TAMPERRTC -
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103ZGH6JTR (ST · BGA-144)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103ZGH6JTR (BGA-144) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103ZGH6JTR (BGA-144) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103ZGH6JTR (BGA-144) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103ZGH6JTR (BGA-144) - 4. Package Dimensions (D×E×A)
BGA-144 · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103ZGH6JTR (BGA-144) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103ZGH6JTR (BGA-144) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32F103
P25 · p25_fig01EXACT PACKAGE
STM32F103ZGH6JTR (BGA-144) — Figure 3. STM32F103xF/G BGA144 ballout
Figure 3. STM32F103xF/G BGA144 ballout
P117 · p117_fig01EXACT PACKAGE
STM32F103ZGH6JTR (BGA-144) — Figure 60. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
Figure 60. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm,
P121 · p121_fig01EXACT PACKAGE
STM32F103ZGH6JTR (BGA-144) — Figure 63. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
Figure 63. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
P1 · p01_fig01881×450px
STM32F103ZGH6JTR (BGA-144) — XL-density performance line ARM®-based 32-bit MCU with 768 KB
XL-density performance line ARM®-based 32-bit MCU with 768 KB
P1 · p01_fig02887×303px
STM32F103ZGH6JTR (BGA-144) — • ECOPACK® packages
• ECOPACK® packages
P111 · p111_fig011546×613px
STM32F103ZGH6JTR (BGA-144) — Figure 56. Typical connection diagram using the ADC
Figure 56. Typical connection diagram using the ADC
P135 · p135_fig011546×1934px
STM32F103ZGH6JTR (BGA-144) — STM32F103xF, STM32F103xG Revision history
STM32F103xF, STM32F103xG Revision history
P111 · p111_fig02All Packages in PDF
STM32F103ZGH6JTR (BGA-144) — Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)

Technical Specifications & Part Details (STM32F103ZGH6JTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103ZGH6JTR (BGA-144) is a 144-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.60 mm (A1=0.30 mm)
Package family: BGA (BGA-144)
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (BGA-144)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.80mm
Pad Size (W × L)Level B
0.30 × 0.30 mm
Pins / Total PadsTopology
144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in (128KB Flash Upgrade)100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103ZGH6JTR (BGA-144)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103ZGH6JTR (BGA-144)?

Manufactured by ST, the STM32F103ZGH6JTR is housed in a BGA-144 package with 144 pins and a 0.80 mm lead pitch. Key pins include: A1 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A5 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103ZGH6JTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103ZGH6JTR (BGA-144) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103ZGH6JTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103ZGH6JTR (ST, BGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
A2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A5PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
A6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
A7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
A8PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A9PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A10PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A11PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A12PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
B1PC14OSC32 IN(5) -_Digital_IOSignal terminal PC14OSC32 IN(5) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14OSC32 IN(5) -_. Supported peripheral buses: RTC/CLK.
B2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
B4PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
B5PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
B7PG15Digital_IOSignal terminal PG15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General.
B8PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
B9PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
B12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DP. Supported peripheral buses: USB, UART, CAN.
C1PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
C2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
C4PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
C5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
C7PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
C8PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
C9PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
C10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
C11NotconnectedDigital_IOSignal terminal Notconnected (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: Notconnected. Supported peripheral buses: General.
C12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DM. Supported peripheral buses: USB, UART, CAN.
D1OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
D2VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
D3VDD_5Power_InPrimary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
D5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
D7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
D8PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
D9PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
D10PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D11PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D12PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
E1OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
E2PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
E3PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
E4PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
E5VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
E6VSS_11GND0V electrical ground return terminal (VSS_11) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSS_10GND0V electrical ground return terminal (VSS_10) for internal core logic, I/O drivers, and analog sub-blocks.
E8PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
E9PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
E10PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
E11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
F1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F2PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC.
F3PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC.
F4VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
ExplorePartsPackagesMFRsUpload