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ATSAML22N18A-CFUT (UFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATSAML22N18A-CFUT

MICROCHIPID: C2055605UFBGA-100 · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATSAML22N18A-CFUT (UFBGA-100)A1PA00A2PB00A3PB30A4VSW0A5VDDCORE01A6PA27A7PC27A8PB23A9PB22A10PA25A11PA24B1PA01B2PB01B3PB02B4PA31B5PA30B6PC28B7PC26B8PC25B9PC24B10PA23B11PA22C1PC02C2PC01C3PB03C4PB31C5RESET#C6GNDIO07C7GNDIO05C8PB25C9PB24C10PA21C11PA20D1PA02D2PC03D3PC00D4VDDIO07-VDDID8VDDIO05D9PB21D10PB19D11PB20E1PB04E2PA03E3GNDANA00E9GNDIO04E10PB17E11PB18F1PB06F2PB05F3VDDANA00L11PA15L10PA13L9PC15L8PB15L7PB13L6VLCD0L5PC13L4PC11L3PC08L2PA09L1PA08K11PA17K10PA14K9PA12K8PB14K7PB12K6PB11K5PC12K4PC10K3PA11K2PC06K1PC05J11PC16J10PA19J9PA16J8PC14J7GNDIO02J6VDDIO02J5PC09J4PA10J3PC07J2PA07J1PA06H11PC18H10PC17H9PA18H8VDDIO03H4GNDANA02H3PA05H2PB09H1PA04G11PC20G10PC19G9GNDIO03G3VDDANA02G2PB07G1PB08F11PB16F10PC21F9VDDIO04Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1A2B2C2D2E2F2G2H2J2K2L2A3B3C3D3E3F3G3H3J3K3L3A4B4C4D4H4J4K4L4A5B5C5J5K5L5A6B6C6J6K6L6A7B7C7J7K7L7A8B8C8D8H8J8K8L8A9B9C9D9E9F9G9H9J9K9L9A10B10C10D10E10F10G10H10J10K10L10A11B11C11D11E11F11G11H11J11K11L11E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA00I/OMultiplexed I/O & Peripheral Pin PA00 (General)
A2PB00I/OMultiplexed I/O & Peripheral Pin PB00 (General)
A3PB30I/OMultiplexed I/O & Peripheral Pin PB30 (General)
A4VSW0I/OMultiplexed I/O & Peripheral Pin VSW0 (General)
A5VDDCORE01PowerPower Supply Input (VDDCORE01 — 1.62V – 3.63V)
A6PA27I/OMultiplexed I/O & Peripheral Pin PA27 (General)
A7PC27I/OMultiplexed I/O & Peripheral Pin PC27 (General)
A8PB23I/OMultiplexed I/O & Peripheral Pin PB23 (General)
A9PB22I/OMultiplexed I/O & Peripheral Pin PB22 (General)
A10PA25I/OMultiplexed I/O & Peripheral Pin PA25 (General)
A11PA24I/OMultiplexed I/O & Peripheral Pin PA24 (General)
B1PA01I/OMultiplexed I/O & Peripheral Pin PA01 (General)
B2PB01I/OMultiplexed I/O & Peripheral Pin PB01 (General)
B3PB02I/OMultiplexed I/O & Peripheral Pin PB02 (General)
B4PA31I/OMultiplexed I/O & Peripheral Pin PA31 (General)
B5PA30I/OMultiplexed I/O & Peripheral Pin PA30 (General)
B6PC28I/OMultiplexed I/O & Peripheral Pin PC28 (General)
B7PC26I/OMultiplexed I/O & Peripheral Pin PC26 (General)
B8PC25I/OMultiplexed I/O & Peripheral Pin PC25 (General)
B9PC24I/OMultiplexed I/O & Peripheral Pin PC24 (General)
B10PA23I/OMultiplexed I/O & Peripheral Pin PA23 (General)
B11PA22I/OMultiplexed I/O & Peripheral Pin PA22 (General)
C1PC02I/OMultiplexed I/O & Peripheral Pin PC02 (General)
C2PC01I/OMultiplexed I/O & Peripheral Pin PC01 (General)
C3PB03I/OMultiplexed I/O & Peripheral Pin PB03 (General)
C4PB31I/OMultiplexed I/O & Peripheral Pin PB31 (General)
C5RESET#ISystem Enable & Hardware Reset (RESET#)
C6GNDIO07GNDGround Reference Pin (GNDIO07)
C7GNDIO05GNDGround Reference Pin (GNDIO05)
C8PB25I/OMultiplexed I/O & Peripheral Pin PB25 (General)
C9PB24I/OMultiplexed I/O & Peripheral Pin PB24 (General)
C10PA21I/OMultiplexed I/O & Peripheral Pin PA21 (General)
C11PA20I/OMultiplexed I/O & Peripheral Pin PA20 (General)
D1PA02I/OMultiplexed I/O & Peripheral Pin PA02 (General)
D2PC03I/OMultiplexed I/O & Peripheral Pin PC03 (General)
D3PC00I/OMultiplexed I/O & Peripheral Pin PC00 (General)
D4VDDIO07-VDDIN01PowerPower Supply Input (VDDIO07-VDDIN01 — 1.62V – 3.63V)
D8VDDIO05PowerPower Supply Input (VDDIO05 — 1.62V – 3.63V)
D9PB21I/OMultiplexed I/O & Peripheral Pin PB21 (General)
D10PB19I/OMultiplexed I/O & Peripheral Pin PB19 (General)
D11PB20I/OMultiplexed I/O & Peripheral Pin PB20 (General)
E1PB04I/OMultiplexed I/O & Peripheral Pin PB04 (General)
E2PA03I/OMultiplexed I/O & Peripheral Pin PA03 (General)
E3GNDANA00GNDGround Reference Pin (GNDANA00)
E9GNDIO04GNDGround Reference Pin (GNDIO04)
E10PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
E11PB18I/OMultiplexed I/O & Peripheral Pin PB18 (General)
F1PB06I/OMultiplexed I/O & Peripheral Pin PB06 (General)
F2PB05I/OMultiplexed I/O & Peripheral Pin PB05 (General)
F3VDDANA00PowerPower Supply Input (VDDANA00 — 1.62V – 3.63V)
F9VDDIO04PowerPower Supply Input (VDDIO04 — 1.62V – 3.63V)
F10PC21I/OMultiplexed I/O & Peripheral Pin PC21 (General)
F11PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
G1PB08I/OMultiplexed I/O & Peripheral Pin PB08 (General)
G2PB07I/OMultiplexed I/O & Peripheral Pin PB07 (General)
G3VDDANA02PowerPower Supply Input (VDDANA02 — 1.62V – 3.63V)
G9GNDIO03GNDGround Reference Pin (GNDIO03)
G10PC19I/OMultiplexed I/O & Peripheral Pin PC19 (General)
G11PC20I/OMultiplexed I/O & Peripheral Pin PC20 (General)
H1PA04I/OMultiplexed I/O & Peripheral Pin PA04 (General)
H2PB09I/OMultiplexed I/O & Peripheral Pin PB09 (General)
H3PA05I/OMultiplexed I/O & Peripheral Pin PA05 (General)
H4GNDANA02GNDGround Reference Pin (GNDANA02)
H8VDDIO03PowerPower Supply Input (VDDIO03 — 1.62V – 3.63V)
H9PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
H10PC17I/OMultiplexed I/O & Peripheral Pin PC17 (General)
H11PC18I/OMultiplexed I/O & Peripheral Pin PC18 (General)
J1PA06I/OMultiplexed I/O & Peripheral Pin PA06 (General)
J2PA07I/OMultiplexed I/O & Peripheral Pin PA07 (General)
J3PC07I/OMultiplexed I/O & Peripheral Pin PC07 (General)
J4PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
J5PC09I/OMultiplexed I/O & Peripheral Pin PC09 (General)
J6VDDIO02PowerPower Supply Input (VDDIO02 — 1.62V – 3.63V)
J7GNDIO02GNDGround Reference Pin (GNDIO02)
J8PC14I/OMultiplexed I/O & Peripheral Pin PC14 (General)
J9PA16I/OMultiplexed I/O & Peripheral Pin PA16 (General)
J10PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
J11PC16I/OMultiplexed I/O & Peripheral Pin PC16 (General)
K1PC05I/OMultiplexed I/O & Peripheral Pin PC05 (General)
K2PC06I/OMultiplexed I/O & Peripheral Pin PC06 (General)
K3PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
K4PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
K5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
K6PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
K7PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
K8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
K10PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
K11PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
L1PA08I/OMultiplexed I/O & Peripheral Pin PA08 (General)
L2PA09I/OMultiplexed I/O & Peripheral Pin PA09 (General)
L3PC08I/OMultiplexed I/O & Peripheral Pin PC08 (General)
L4PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
L5PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
L6VLCD0I/OMultiplexed I/O & Peripheral Pin VLCD0 (General)
L7PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
L8PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
L9PC15I/OMultiplexed I/O & Peripheral Pin PC15 (General)
L10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
L11PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
PIN A1 PA00
I/O
Multiplexed I/O & Peripheral Pin PA00 (General)
Design note: Signal terminal PA00 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA00. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATSAML22N18A-CFUT (MICROCHIP · UFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATSAML22N18A-CFUT (UFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATSAML22N18A-CFUT (UFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATSAML22N18A-CFUT (UFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATSAML22N18A-CFUT (UFBGA-100) - 4. Package Dimensions (D×E×A)
UFBGA-100 · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATSAML22N18A-CFUT (UFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATSAML22N18A-CFUT (UFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for ATSAML22N16A / ATSAML22N18A
P25 · p25_fig01EXACT PACKAGE
ATSAML22N18A-CFUT (UFBGA-100) — Figure 4-4. UFBGA100
Figure 4-4. UFBGA100
P1 · p01_fig01456×280px
ATSAML22N18A-CFUT (UFBGA-100) — 32-bit ARM Cortex-M0+ Ultra-Low-Power MCU family with Peripheral Touch Controller (PTC), Segment LCD
32-bit ARM Cortex-M0+ Ultra-Low-Power MCU family with Peripheral Touch Controller (PTC), Segment LCD
P25 · p25_fig01P25
ATSAML22N18A-CFUT (UFBGA-100) — Datasheet Page 25 (p25_fig01)
Datasheet Page 25 (p25_fig01)
P465 · p465_fig011478×828px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 28-4. I/O configuration - Standard Input
Figure 28-4. I/O configuration - Standard Input
P465 · p465_fig02871×755px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 28-4. I/O configuration - Standard Input
Figure 28-4. I/O configuration - Standard Input
P1057 · p1057_fig011929×774px
ATSAML22N18A-CFUT (UFBGA-100) — A maximum of three reflow passes is allowed per component.
A maximum of three reflow passes is allowed per component.
P1057 · p1057_fig01P1057
ATSAML22N18A-CFUT (UFBGA-100) — Datasheet Page 1057 (p1057_fig01)
Datasheet Page 1057 (p1057_fig01)
P1062 · p1062_fig011294×849px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 47-5. External Analog Reference Schematic With One Reference
Figure 47-5. External Analog Reference Schematic With One Reference
P1062 · p1062_fig021775×1301px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 47-5. External Analog Reference Schematic With One Reference
Figure 47-5. External Analog Reference Schematic With One Reference
P1062 · p1062_fig02P1062
ATSAML22N18A-CFUT (UFBGA-100) — Datasheet Page 1062 (p1062_fig02)
Datasheet Page 1062 (p1062_fig02)
P1063 · p1063_fig01957×912px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 47-6. External Reset Circuit Schematic
Figure 47-6. External Reset Circuit Schematic
P1063 · p1063_fig02957×912px
ATSAML22N18A-CFUT (UFBGA-100) — Figure 47-7. External Reset Circuit Schematic (EFT Immunity Enhancement)
Figure 47-7. External Reset Circuit Schematic (EFT Immunity Enhancement)
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (ATSAML22N18A-CFUT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATSAML22N18A-CFUT (UFBGA-100) is a 100-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 0.58 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.62V – 3.63V supply operation across -40°C to +85°C with integrated USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
1.62V – 3.63V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 0.58 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.58mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATSAML22N18A-CFUT (UFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATSAML22N18A-CFUT (UFBGA-100)?

Manufactured by MICROCHIP, the ATSAML22N18A-CFUT is housed in a UFBGA-100 package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.62V – 3.63V. Key pins include: A1 (PA00: Multiplexed I/O & Peripheral Pin PA00 (General)), A2 (PB00: Multiplexed I/O & Peripheral Pin PB00 (General)), A3 (PB30: Multiplexed I/O & Peripheral Pin PB30 (General)), A4 (VSW0: Multiplexed I/O & Peripheral Pin VSW0 (General)), A5 (VDDCORE01: Power Supply Input (VDDCORE01 — 1.62V – 3.63V)), A6 (PA27: Multiplexed I/O & Peripheral Pin PA27 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATSAML22N18A-CFUT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATSAML22N18A-CFUT (UFBGA-100) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATSAML22N18A-CFUT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATSAML22N18A-CFUT (MICROCHIP, UFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & ATSAML22N16A / ATSAML22N18A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA00Digital_IOSignal terminal PA00 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA00. Supported peripheral buses: General.
A2PB00Digital_IOSignal terminal PB00 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB00. Supported peripheral buses: General.
A3PB30Digital_IOSignal terminal PB30 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB30. Supported peripheral buses: General.
A4VSW0Digital_IOSignal terminal VSW0 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: VSW0. Supported peripheral buses: General.
A5VDDCORE01Power_InPrimary positive power supply input (VDDCORE01) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
A6PA27Digital_IOSignal terminal PA27 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA27. Supported peripheral buses: General.
A7PC27Digital_IOSignal terminal PC27 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC27. Supported peripheral buses: General.
A8PB23Digital_IOSignal terminal PB23 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB23. Supported peripheral buses: General.
A9PB22Digital_IOSignal terminal PB22 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB22. Supported peripheral buses: General.
A10PA25Digital_IOSignal terminal PA25 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA25. Supported peripheral buses: General.
A11PA24Digital_IOSignal terminal PA24 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA24. Supported peripheral buses: General.
B1PA01Digital_IOSignal terminal PA01 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA01. Supported peripheral buses: General.
B2PB01Digital_IOSignal terminal PB01 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB01. Supported peripheral buses: General.
B3PB02Digital_IOSignal terminal PB02 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB02. Supported peripheral buses: General.
B4PA31Digital_IOSignal terminal PA31 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA31. Supported peripheral buses: General.
B5PA30Digital_IOSignal terminal PA30 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA30. Supported peripheral buses: General.
B6PC28Digital_IOSignal terminal PC28 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC28. Supported peripheral buses: General.
B7PC26Digital_IOSignal terminal PC26 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC26. Supported peripheral buses: General.
B8PC25Digital_IOSignal terminal PC25 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC25. Supported peripheral buses: General.
B9PC24Digital_IOSignal terminal PC24 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC24. Supported peripheral buses: General.
B10PA23Digital_IOSignal terminal PA23 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA23. Supported peripheral buses: General.
B11PA22Digital_IOSignal terminal PA22 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA22. Supported peripheral buses: General.
C1PC02Digital_IOSignal terminal PC02 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC02. Supported peripheral buses: General.
C2PC01Digital_IOSignal terminal PC01 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC01. Supported peripheral buses: General.
C3PB03Digital_IOSignal terminal PB03 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB03. Supported peripheral buses: General.
C4PB31Digital_IOSignal terminal PB31 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB31. Supported peripheral buses: General.
C5RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
C6GNDIO07GND0V electrical ground return terminal (GNDIO07) for internal core logic, I/O drivers, and analog sub-blocks.
C7GNDIO05GND0V electrical ground return terminal (GNDIO05) for internal core logic, I/O drivers, and analog sub-blocks.
C8PB25Digital_IOSignal terminal PB25 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB25. Supported peripheral buses: General.
C9PB24Digital_IOSignal terminal PB24 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB24. Supported peripheral buses: General.
C10PA21Digital_IOSignal terminal PA21 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA21. Supported peripheral buses: General.
C11PA20Digital_IOSignal terminal PA20 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA20. Supported peripheral buses: General.
D1PA02Digital_IOSignal terminal PA02 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA02. Supported peripheral buses: General.
D2PC03Digital_IOSignal terminal PC03 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC03. Supported peripheral buses: General.
D3PC00Digital_IOSignal terminal PC00 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC00. Supported peripheral buses: General.
D4VDDIO07-VDDIN01Power_InPrimary positive power supply input (VDDIO07-VDDIN01) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
D8VDDIO05Power_InPrimary positive power supply input (VDDIO05) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
D9PB21Digital_IOSignal terminal PB21 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB21. Supported peripheral buses: General.
D10PB19Digital_IOSignal terminal PB19 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB19. Supported peripheral buses: General.
D11PB20Digital_IOSignal terminal PB20 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB20. Supported peripheral buses: General.
E1PB04Digital_IOSignal terminal PB04 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB04. Supported peripheral buses: General.
E2PA03Digital_IOSignal terminal PA03 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA03. Supported peripheral buses: General.
E3GNDANA00GND0V electrical ground return terminal (GNDANA00) for internal core logic, I/O drivers, and analog sub-blocks.
E9GNDIO04GND0V electrical ground return terminal (GNDIO04) for internal core logic, I/O drivers, and analog sub-blocks.
E10PB17Digital_IOSignal terminal PB17 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
E11PB18Digital_IOSignal terminal PB18 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB18. Supported peripheral buses: General.
F1PB06Digital_IOSignal terminal PB06 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB06. Supported peripheral buses: General.
F2PB05Digital_IOSignal terminal PB05 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB05. Supported peripheral buses: General.
F3VDDANA00Power_InPrimary positive power supply input (VDDANA00) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
F9VDDIO04Power_InPrimary positive power supply input (VDDIO04) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
F10PC21Digital_IOSignal terminal PC21 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC21. Supported peripheral buses: General.
F11PB16Digital_IOSignal terminal PB16 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
G1PB08Digital_IOSignal terminal PB08 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB08. Supported peripheral buses: General.
G2PB07Digital_IOSignal terminal PB07 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB07. Supported peripheral buses: General.
G3VDDANA02Power_InPrimary positive power supply input (VDDANA02) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
G9GNDIO03GND0V electrical ground return terminal (GNDIO03) for internal core logic, I/O drivers, and analog sub-blocks.
G10PC19Digital_IOSignal terminal PC19 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC19. Supported peripheral buses: General.
G11PC20Digital_IOSignal terminal PC20 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PC20. Supported peripheral buses: General.
H1PA04Digital_IOSignal terminal PA04 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA04. Supported peripheral buses: General.
H2PB09Digital_IOSignal terminal PB09 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PB09. Supported peripheral buses: General.
H3PA05Digital_IOSignal terminal PA05 (I/O, 1.62V – 3.63V domain). Multiplexed alternate functions: PA05. Supported peripheral buses: General.
H4GNDANA02GND0V electrical ground return terminal (GNDANA02) for internal core logic, I/O drivers, and analog sub-blocks.
H8VDDIO03Power_InPrimary positive power supply input (VDDIO03) operating in the 1.62V – 3.63V domain (Max rating: 3.63V).
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