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STM32F051R8H7TR (UFBGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F051R8H7TR

STID: C2055232UFBGA-64 · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F051R8H7TR (UFBGA-64)A1PC14-OSC32_IA2PC13A3PB9A4PB4A5PB3A6PA15A7PA14 (SWCLK)A8PA13 (SWDIO)B1PC15-OSC32_OB2VBATB3PB8B4BOOT0B5PD2B6PC11B7PC10B8PA12C1PF0-OSC_IN(PC2PF4C3PB7C4PB5C5PC12C6PA10C7PA9C8PA11D1PF1-OSC_OUT(D2PF5D3PB6D4VSSD5VSSD6PF6D7PA8D8PC9H8PB12H7PB11H6PC5H5PC4H4PA7H3PA4H2PA1H1VDDAG8PB13G7PB10G6PB2G5PB1G4PA6G3PA3G2PA0G1PC3F8PB14F7PB15F6PC6F5PB0F4PA5F3PA2F2PC2F1VSSAE8PC8E7PC7E6PF7E5VDDE4VDDE3PC0E2PC1E1NRSTGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8C1C2C3C4C5C6C7C8D1D2D3D4D5D6D7D8E1E2E3E4E5E6E7E8F1F2F3F4F5F6F7F8G1G2G3G4G5G6G7G8H1H2H3H4H5H6H7H8E=5.00mm · Pitch e=0.50mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14-OSC32_IN(PC14)I/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN(PC14) (RTC/CLK)
A2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
A3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
A4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
A5PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
A6PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
A7PA14 (SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)
A8PA13 (SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
B1PC15-OSC32_OUT(PC15)I/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT(PC15) (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B4BOOT0IInput-Only Pin BOOT0 (General)
B5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B6PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B7PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B8PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
C1PF0-OSC_IN(PF0)I/OMultiplexed I/O & Peripheral Pin PF0-OSC_IN(PF0) (RTC/CLK)
C2PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
C3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
C5PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
C6PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
C7PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
C8PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM)
D1PF1-OSC_OUT(PF1)I/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT(PF1) (RTC/CLK)
D2PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
D3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
D4VSSGNDGround Reference Pin (VSS)
D5VSSGNDGround Reference Pin (VSS)
D6PF6I/OMultiplexed I/O & Peripheral Pin PF6 (I2C)
D7PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
D8PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
E3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
E4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E6PF7I/OMultiplexed I/O & Peripheral Pin PF7 (I2C)
E7PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
E8PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
F1VSSAGNDGround Reference Pin (VSSA)
F2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
F3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
F4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
F6PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
F7PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
F8PB14I/OMultiplexed I/O & Peripheral Pin PB14 (SPI, PWM)
G1PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
G2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
G3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
G4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
G5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
G6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
G7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (I2C, PWM)
G8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (SPI, PWM)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
H3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
H4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
H5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
H6PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
H7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
H8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI)
PIN A1 PC14-OSC32_IN(PC14)
I/O
Multiplexed I/O & Peripheral Pin PC14-OSC32_IN(PC14) (RTC/CLK)
Design note: Signal terminal PC14-OSC32_IN(PC14) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN(PC14). Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F051R8H7TR (ST · UFBGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F051R8H7TR (UFBGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F051R8H7TR (UFBGA-64) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F051R8H7TR (UFBGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F051R8H7TR (UFBGA-64) - 4. Package Dimensions (D×E×A)
UFBGA-64 · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F051R8H7TR (UFBGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F051R8H7TR (UFBGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32F051
P28 · p28_fig01EXACT PACKAGE
STM32F051R8H7TR (UFBGA-64) — Figure 4. UFBGA64 package pinout        
Figure 4. UFBGA64 package pinout        
P91 · p91_fig01EXACT PACKAGE
STM32F051R8H7TR (UFBGA-64) — Figure 34. UFBGA64 package outline
Figure 34. UFBGA64 package outline
P92 · p92_fig01EXACT PACKAGE
STM32F051R8H7TR (UFBGA-64) — Figure 35. Recommended footprint for UFBGA64 package
Figure 35. Recommended footprint for UFBGA64 package
P1 · p01_fig011238×483px
STM32F051R8H7TR (UFBGA-64) — • CRC calculation unit
• CRC calculation unit
P1 · p01_fig02888×340px
STM32F051R8H7TR (UFBGA-64) — • All packages ECOPACK®2
• All packages ECOPACK®2
P28 · p28_fig021546×955px
STM32F051R8H7TR (UFBGA-64) — Figure 5. LQFP48 package pinout
Figure 5. LQFP48 package pinout
P28 · p28_fig01P28
STM32F051R8H7TR (UFBGA-64) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)
P29 · p29_fig011546×1112px
STM32F051R8H7TR (UFBGA-64) — Figure 6. UFQFPN48 package pinout
Figure 6. UFQFPN48 package pinout
P29 · p29_fig021546×993px
STM32F051R8H7TR (UFBGA-64) — Figure 7. WLCSP36 package pinout
Figure 7. WLCSP36 package pinout
P31 · p31_fig011696×1197px
STM32F051R8H7TR (UFBGA-64) — DocID022265 Rev 7 31/122
DocID022265 Rev 7 31/122
P43 · p43_fig011546×1399px
STM32F051R8H7TR (UFBGA-64) — Figure 13. Power supply scheme
Figure 13. Power supply scheme
P43 · p43_fig01P43
STM32F051R8H7TR (UFBGA-64) — Datasheet Page 43 (p43_fig01)
Datasheet Page 43 (p43_fig01)
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32F051R8H7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F051R8H7TR (UFBGA-64) is a 64-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.53 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
34 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
64P / 64Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F051R8H7TR (UFBGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F051R8H7TR (UFBGA-64)?

Manufactured by ST, the STM32F051R8H7TR is housed in a UFBGA-64 package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0 V to 3.6 V. Key pins include: A1 (PC14-OSC32_IN(PC14): Multiplexed I/O & Peripheral Pin PC14-OSC32_IN(PC14) (RTC/CLK)), A2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), A3 (PB9: Multiplexed I/O & Peripheral Pin PB9 (I2C)), A4 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, PWM)), A5 (PB3: Multiplexed I/O & Peripheral Pin PB3 (SPI, PWM)), A6 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32F051R8H7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F051R8H7TR (UFBGA-64) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F051R8H7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F051R8H7TR (ST, UFBGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F051 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14-OSC32_IN(PC14)Digital_IOSignal terminal PC14-OSC32_IN(PC14) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN(PC14). Supported peripheral buses: RTC/CLK.
A2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
A3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
A4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, PWM.
A5PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, PWM.
A6PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
A7PA14 (SWCLK)Digital_IOSignal terminal PA14 (SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (SWCLK). Supported peripheral buses: UART, SWD/JTAG.
A8PA13 (SWDIO)Digital_IOSignal terminal PA13 (SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (SWDIO). Supported peripheral buses: SWD/JTAG.
B1PC15-OSC32_OUT(PC15)Digital_IOSignal terminal PC15-OSC32_OUT(PC15) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT(PC15). Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
B5PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B6PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B7PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B8PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
C1PF0-OSC_IN(PF0)Digital_IOSignal terminal PF0-OSC_IN(PF0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN(PF0). Supported peripheral buses: RTC/CLK.
C2PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
C3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
C5PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
C6PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
C7PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
C8PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
D1PF1-OSC_OUT(PF1)Digital_IOSignal terminal PF1-OSC_OUT(PF1) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT(PF1). Supported peripheral buses: RTC/CLK.
D2PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
D3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
D4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: I2C.
D7PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
D8PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
E3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C.
E7PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
E8PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
F1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
F3PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
F4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
F6PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
F7PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
F8PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, PWM.
G1PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
G2PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
G3PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
G4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
G5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
G6PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
G7PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: I2C, PWM.
G8PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, PWM.
H1VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
H3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
H4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
H5PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
H6PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
H7PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM.
H8PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
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