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STM32L052T8Y6TR (WLCSP-36) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L052T8Y6TR

STID: C2053835WLCSP-36 · 36 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L052T8Y6TR (WLCSP-36)A1PA13A2PA15A3PB4A4PB7A5VDDA6PC14 - OSC32B1PA12B2PA14B3PB3B4PB6B5PB8B6IOB6C1PA10C2PA11C3PB1C4PB5C5BOOT0C6NRSTF6PA1F5PA3F4PA5F3PA7F2PB2F1VDDE6VREF+E5PA2E4PA4E3PA6E2PB10E1PA8D6VSSD5VDDAD4PA0D3PB0D2PB11D1PA9Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
A1B1C1D1E1F1A2B2C2D2E2F2A3B3C3D3E3F3A4B4C4D4E4F4A5B5C5D5E5F5A6B6C6D6E6F6E=2.60mm · Pitch e=0.40mmD=2.90mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.60mm × 2.90mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (36/36)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA13I/OMultiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
A3PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI)
A4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
A5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A6PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
B1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
B2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG)
B3PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
B4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B6IOB6I/OGeneral Purpose Digital I/O Pin IOB6
C1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
C2PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
C3PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC)
C4PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
C5BOOT0IInput-Only Pin BOOT0 (General)
C6NRSTISystem Enable & Hardware Reset (NRST)
D1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, RTC/CLK)
D2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
D3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC)
D4PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
D5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
D6VSSGNDGround Reference Pin (VSS)
E1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (USB, UART, RTC/CLK)
E2PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C, PWM)
E3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
E4PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
E5PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
E6VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
F1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F2PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
F3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
F4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
F5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
F6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
PIN A1 PA13
I/O
Multiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)
Design note: Alt: SWDIO USB NOE ,_
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L052T8Y6TR (ST · WLCSP-36)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L052T8Y6TR (WLCSP-36) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L052T8Y6TR (WLCSP-36) - 2. Standard Pinout (Top View)
True package pinout (36 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L052T8Y6TR (WLCSP-36) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L052T8Y6TR (WLCSP-36) - 4. Package Dimensions (D×E×A)
WLCSP-36 · 2.60×2.90mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L052T8Y6TR (WLCSP-36) - 5. Recommended Land Pattern
IPC-7351B Footprint (36 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L052T8Y6TR (WLCSP-36) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32L052
P41 · p41_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 7. STM32L052x6/8 WLCSP36 ballout
Figure 7. STM32L052x6/8 WLCSP36 ballout
P128 · p128_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 51. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
Figure 51. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
P129 · p129_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 52. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
Figure 52. Standard WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
P131 · p131_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 54. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
Figure 54. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
P132 · p132_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 55. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
Figure 55. Thin WLCSP36 - 2.61 x 2.88 mm, 0.4 mm pitch wafer level chip scale
P133 · p133_fig01EXACT PACKAGE
STM32L052T8Y6TR (WLCSP-36) — Figure 56. Standard WLCSP36 marking example (package top view)
Figure 56. Standard WLCSP36 marking example (package top view)
P1 · p01_fig01886×511px
STM32L052T8Y6TR (WLCSP-36) — Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 64 KB
Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 64 KB
P41 · p41_fig021546×1157px
STM32L052T8Y6TR (WLCSP-36) — Figure 8. STM32L052x6/8 LQFP32 pinout
Figure 8. STM32L052x6/8 LQFP32 pinout
P41 · p41_fig01P41
STM32L052T8Y6TR (WLCSP-36) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P55 · p55_fig011751×1623px
STM32L052T8Y6TR (WLCSP-36) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P55 · p55_fig021873×770px
STM32L052T8Y6TR (WLCSP-36) — Figure 13. Current consumption measurement scheme
Figure 13. Current consumption measurement scheme
P55 · p55_fig01P55
STM32L052T8Y6TR (WLCSP-36) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32L052T8Y6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L052T8Y6TR (WLCSP-36) is a 36-pin embedded microcontroller unit (mcu) featuring a 2.90 × 2.60 × 0.59 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
25 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.90 × 2.60 × 0.59 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-36)
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol36 auto-grouped pins
OK
IPC-7351B Land Pattern36 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-36)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.90 × 2.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.59mm · e=0.40mm
Pad Size (W × L)Level B
0.16 × 0.16 mm
Pins / Total PadsTopology
36P / 36Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-36
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L052T8Y6TR (WLCSP-36)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L052T8Y6TR (WLCSP-36)?

Manufactured by ST, the STM32L052T8Y6TR is housed in a WLCSP-36 package with 36 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: A1 (PA13: Multiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)), A3 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)), A5 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A6 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L052T8Y6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L052T8Y6TR (WLCSP-36) has a nominal body envelope of 2.60 × 2.90 mm, pitch e = 0.40 mm, and 36 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L052T8Y6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L052T8Y6TR (ST, WLCSP-36) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (36 pins) & STM32L052 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB, SWD/JTAG.
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
A3PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI.
A4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
A5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A6PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
B1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI.
B2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG.
B3PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, PWM.
B4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B6IOB6Digital_IOGeneral Purpose Digital I/O Pin IOB6
C1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
C2PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI.
C3PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC.
C4PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C.
C5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
C6NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, RTC/CLK.
D2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM.
D3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC.
D4PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
D5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: USB, UART, RTC/CLK.
E2PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK, I2C2_SCL. Supported peripheral buses: SPI, I2C, PWM.
E3PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
E4PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
E5PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
E6VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F2PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
F3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
F4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
F5PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
F6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
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