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STM32F051K8U7TR (UFQFPN-32(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F051K8U7TR

STID: C2053268UFQFPN-32(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F051K8U7TR (UFQFPN-32(5x5))1VDD2PF0-OSC_IN3PF1-OSC_OUT4NRST5VDDA616 -Dec-20157PA18PA29PA310PA411PA512PA613PA714PB015PB116PB217VDD33VSS32PB831BOOT030PB729PB628PB527PB426PB325PA1524PA14 (SWCLK)23PA13 (SWDIO)22PA1221PA1120PA1019PA918PA8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
2PF0-OSC_INI/OMultiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK)
3PF1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)
4NRSTISystem Enable & Hardware Reset (NRST)
5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
616 -Dec-2015I/OMultiplexed I/O & Peripheral Pin 16 -Dec-2015 (SPI)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
14PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
15PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
16PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
17VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
18PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
19PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, PWM)
20PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, PWM)
21PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM)
22PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
23PA13 (SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
24PA14 (SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)
25PA15I/OMultiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
26PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
27PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, PWM)
28PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
29PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
30PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
31BOOT0IInput-Only Pin BOOT0 (General)
32PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
33VSSGNDGround Reference Pin (VSS)
PIN 1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Alt: Digitalpowersupply
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 17 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F051K8U7TR (ST · UFQFPN-32(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F051K8U7TR (UFQFPN-32(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F051K8U7TR (UFQFPN-32(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F051K8U7TR (UFQFPN-32(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F051K8U7TR (UFQFPN-32(5x5)) - 4. Package Dimensions (D×E×A)
UFQFPN-32(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F051K8U7TR (UFQFPN-32(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F051K8U7TR (UFQFPN-32(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (17 figures · Page 1/2)
Showing 1–12 of 17 uncropped original figures for STM32F051
P30 · p30_fig01EXACT PACKAGE
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 8. LQFP32 package pinout
Figure 8. LQFP32 package pinout
P30 · p30_fig02EXACT PACKAGE
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 9. UFQFPN32 package pinout
Figure 9. UFQFPN32 package pinout
P109 · p109_fig01EXACT PACKAGE
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 52. UFQFPN32 package outline '
Figure 52. UFQFPN32 package outline '
P110 · p110_fig01EXACT PACKAGE
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 53. Recommended footprint for UFQFPN32 package
Figure 53. Recommended footprint for UFQFPN32 package
P1 · p01_fig011238×483px
STM32F051K8U7TR (UFQFPN-32(5x5)) — • CRC calculation unit
• CRC calculation unit
P1 · p01_fig02888×340px
STM32F051K8U7TR (UFQFPN-32(5x5)) — • All packages ECOPACK®2
• All packages ECOPACK®2
P43 · p43_fig011546×1399px
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 13. Power supply scheme
Figure 13. Power supply scheme
P43 · p43_fig01P43
STM32F051K8U7TR (UFQFPN-32(5x5)) — Datasheet Page 43 (p43_fig01)
Datasheet Page 43 (p43_fig01)
P62 · p62_fig011546×718px
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 17. Typical application with an 8 MHz crystal
Figure 17. Typical application with an 8 MHz crystal
P79 · p79_fig011751×902px
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 25. ADC accuracy characteristics
Figure 25. ADC accuracy characteristics
P79 · p79_fig021546×667px
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 26. Typical connection diagram using the ADC
Figure 26. Typical connection diagram using the ADC
P92 · p92_fig011546×1051px
STM32F051K8U7TR (UFQFPN-32(5x5)) — Figure 35. Recommended footprint for UFBGA64 package
Figure 35. Recommended footprint for UFBGA64 package
Page 1 / 2 (17 extracted figures)

Technical Specifications & Part Details (STM32F051K8U7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F051K8U7TR (UFQFPN-32(5x5)) is a 32-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 0.55 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
15 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-32(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.50×3.50mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-32(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-32(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F051K8U7TR (UFQFPN-32(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F051K8U7TR (UFQFPN-32(5x5))?

Manufactured by ST, the STM32F051K8U7TR is housed in a UFQFPN-32(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0 V to 3.6 V. Key pins include: 1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 2 (PF0-OSC_IN: Multiplexed I/O & Peripheral Pin PF0-OSC_IN (RTC/CLK)), 3 (PF1-OSC_OUT: Multiplexed I/O & Peripheral Pin PF1-OSC_OUT (RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (16 -Dec-2015: Multiplexed I/O & Peripheral Pin 16 -Dec-2015 (SPI)).

What are the IPC-7351B PCB Footprint dimensions for STM32F051K8U7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F051K8U7TR (UFQFPN-32(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F051K8U7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F051K8U7TR (ST, UFQFPN-32(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & STM32F051 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PF0-OSC_INDigital_IOSignal terminal PF0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0-OSC_IN. Supported peripheral buses: RTC/CLK.
3PF1-OSC_OUTDigital_IOSignal terminal PF1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1-OSC_OUT. Supported peripheral buses: RTC/CLK.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
616 -Dec-2015Digital_IOSignal terminal 16 -Dec-2015 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPIS. Supported peripheral buses: SPI.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
14PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
15PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
16PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
19PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM.
20PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, PWM.
21PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
22PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
23PA13 (SWDIO)Digital_IOSignal terminal PA13 (SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (SWDIO). Supported peripheral buses: SWD/JTAG.
24PA14 (SWCLK)Digital_IOSignal terminal PA14 (SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (SWCLK). Supported peripheral buses: UART, SWD/JTAG.
25PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
26PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, PWM.
27PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, PWM.
28PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
29PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
30PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
31BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
32PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
33VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
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